Semiconductor device

Abstract

The invention discloses a semiconductor device. The semiconductor device comprises a substrate, an electrostatic discharge protection polysilicon layer, an insulating layer, a metal layer, a first contact part and a second contact part. The substrate defines a gate pad region. The electrostatic discharge protection polysilicon layer is disposed over the gate pad region of the substrate and is electrically isolated from the substrate. The electrostatic discharge protection polysilicon layer comprises a first doped region, a second doped region, a third doped region and a fourth doped region, wherein the first doped region, the second doped region and the third doped region have first electrical properties and the fourth doped region has second electrical properties. The first doped region is located at the periphery of the gate pad region and is connected with the second doped region. The fourth doped region is arranged between the first doped region and the third doped region. The metal layer comprises a first part and a second part, and an isolation part is arranged between the two parts. The first contact part and the second contact part are arranged in the insulating layer and are electrically connected with the first doped region and the first part as well as the third doped region and the second part respectively; the semiconductor device of the present invention can moreefficiently dredge the electrostatic discharge current and prevent the path of the electrostatic discharge current from being excessively concentrated.

Description

technical field [0001] The present invention relates to semiconductor components, in particular to a semiconductor component with electrostatic discharge protection function. Background technique [0002] Existing semiconductor elements with electrostatic discharge protection function, taking metal oxide half field effect transistor switching element as an example, the electrostatic discharge protection element is usually arranged around the source or drain with a large area, this configuration will make The ESD current passes through peripheral circuits, resulting in a longer ESD response time and complicating component design. [0003] Therefore, in the prior art, the electrostatic discharge protection element is arranged in the gate pad area of ​​the semiconductor element. The design is relatively simple, but since the gate pad area is relatively smaller than the source / drain pad area, the protection provided by the ESD protection device is quite limited. [0004] Pleas...

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Problems solved by technology

[0008] In view of this, the present invention provides a semico

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