Instruction processing method and storage controller
A storage controller and instruction processing technology, applied in register device, program control design, electrical digital data processing, etc., can solve problems such as affecting the processing capacity of the processor, large bus delay, etc.
Active Publication Date: 2019-12-27
SHENZHEN EPOSTAR ELECTRONICS LTD
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- Application Information
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Problems solved by technology
However, since all elements of the memory controller 100 are attached to the system bus 120, this creates a considerable bus delay
This bus delay can seriously affect the throughput of the processor
Method used
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Embodiment Construction
[0038] figure 2 It is a block diagram of a storage controller according to an embodiment of the present invention.
[0039] Please refer to figure 2 The storage controller 200 of an embodiment of the present invention includes a processor 210 and peripheral elements 240(1)-240(N). The processor 210 is coupled to peripheral elements 240(1)-240(N) through the system bus 220. The processor 210 includes a processor core 211 and an instruction buffer 230. The processor core 211 is coupled to the instruction buffer 230 through the regional bus 260. When the processor core 211 issues an instruction, the instruction is transmitted to the instruction buffer 230 via the instruction path 201. The instruction buffer 230 is, for example, a static random access memory (SRAM), a cache memory (cache memory) or other similar elements. The peripheral components 240(1)-240(N) will access instructions from the instruction buffer 230 and execute the instructions. Since the delay of the local bu...
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The invention provides an instruction processing method and a storage controller. The instruction processing method is suitable for the storage controller. The storage controller comprises a processorand peripheral elements. The instruction processing method comprises the following steps: configuring a first instruction buffer and a second instruction buffer in a processor; configuring a synchronizer in the storage controller, the synchronizer changing a value of the flag at a predetermined time interval to set the first instruction buffer or the second instruction buffer to be valid; and when the first instruction buffer is valid and the processor issues an instruction, the processor temporarily storing the instruction in the first instruction buffer and one of the peripheral elements accessing the instruction in the first instruction buffer to execute a corresponding operation. Therefore, the instruction processing method and the storage controller provided by the invention can effectively reduce the bus delay and improve the instruction execution speed.
Description
Technical field [0001] The invention relates to an instruction processing method and a storage controller, in particular to an instruction processing method and a storage controller capable of improving the execution speed of instructions. Background technique [0002] figure 1 It is a block diagram of a known storage controller. in figure 1 Among them, the memory controller 100 has a processor 110, a system bus 120, an instruction buffer 130, and peripheral elements 140(1)-140(N). When the processor 110 issues an instruction, the instruction is transferred from the instruction path 101 to the instruction buffer 130 and temporarily stored in the instruction buffer 130. Peripheral components 140(1)-140(N) can access and execute instructions in the instruction buffer 130 through the system bus 120. However, since all the components of the memory controller 100 are attached to the system bus 120, this causes a considerable bus delay. This bus delay will seriously affect the throu...
Claims
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Login to View More IPC IPC(8): G06F9/30
CPCG06F9/30047G06F9/30098
Inventor 陈灿琳
Owner SHENZHEN EPOSTAR ELECTRONICS LTD