Butt coupling method used for monolithic integrated chip

A single-chip integration and docking coupling technology, which is applied in the field of docking coupling, can solve the problems of low coupling efficiency affecting the optical power of the device, affecting the transmission characteristics of the device, and poor refractive index, so as to improve the quality of docking coupling, improve growth quality, and reduce loss. Effect

Active Publication Date: 2020-01-21
湖北光安伦芯片有限公司
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Problems solved by technology

Traditional docking methods, such as the patent US7018861B2, cannot solve two major problems. One is that the thickness of the materials in different functional areas is inconsistent, and the centers of the active areas of the two need to be completely aligned to avoid the mismatch of optical fields in different functional areas, which will cause low cou

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  • Butt coupling method used for monolithic integrated chip
  • Butt coupling method used for monolithic integrated chip
  • Butt coupling method used for monolithic integrated chip

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Embodiment Construction

[0040] The solutions of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0041] This embodiment discloses a butt coupling method for monolithic integrated chips, including the following steps:

[0042] S1) if figure 1 , growing the first functional device on the substrate 1, including sequentially growing the first InP buffer layer 2, the quaternary optical field control layer 3, the second InP buffer layer 4, the first lower waveguide layer 5, and the first active quantum well Layer 6, first upper waveguide layer 7, first InP cladding layer 8;

[0043] Among them, the material composition of the quaternary optical field control layer 3 is 120-180nm different from the PL of the active MQW, and its function is to control the optical field of the first functional device in the active / passive waveguide of the second functional device to avoid The light leakage of the substrate can be used as an etching stop l...

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Abstract

The invention discloses a butt coupling method used for a monolithic integrated chip. The method comprises the following steps of S1, generating a first active functional device on a substrate, dividing an InP buffer layer into two parts by the device through a light field control layer, and realizing complete alignment of an active region center of the first functional device and an active regioncenter of a second functional device by controlling a growth thickness of a second buffer layer; S2, depositing a dielectric film, defining the second functional device through lithography etching, and reducing reflection at an interface of the first functional device and the second functional device through a certain angle between a tail end of a mask and an optical waveguide direction; S3, removing a partial region of the first functional device by adopting an etching and selective corrosion method; S4, carrying out high-temperature heat treatment on the first functional device to form a smooth side wall interface and an undercut with a certain length; and S5, growing the second functional device in a butt joint manner. Coupling efficiency is high, and a transmission characteristic is good.

Description

technical field [0001] The invention relates to monolithic integrated chip technology, in particular to a butt coupling method for monolithic integrated chips, which is used in the manufacturing process of monolithic integrated chips. Background technique [0002] The main purpose of monolithic photonic integrated chips is to monolithically integrate at least two functional devices, including integration between active devices, such as semiconductor lasers, semiconductor optical amplifiers, electroabsorber modulators, semiconductor photodetectors, and Integration of active and passive devices, such as optical waveguides, multimode interferometers, mode spot converters, gratings, etc. Compared with discrete devices, monolithic integrated devices can complete more complex functions than discrete devices through the combination of components, which greatly reduces the coupling cost and packaging cost of different devices, and is excellent in optical, electrical performance, sta...

Claims

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Application Information

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IPC IPC(8): H01S5/026
CPCH01S5/0261H01S2304/04
Inventor 王汉华黄爽许海明刘建军唐琦
Owner 湖北光安伦芯片有限公司
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