Integrated circuit chip and test method of fuse

Abstract

The invention relates to an integrated circuit chip and a test method of a fuse. The chip comprises a substrate, a plurality of conductive layers, a dielectric layer, the fuse and a latch circuit, wherein the dielectric layer is arranged between the adjacent conductive layers, the dielectric layer is arranged between the substrate and the conductive layer adjacent to the substrate, a contact holeis formed in the dielectric layer, the fuse is located on the first conductive layers, the first conductive layers are the uppermost conductive layer in the multiple conductive layers, the portion close to the substrate is the bottom layer, the portion far away from the substrate is the upper layer, the latch circuit is disposed on the substrate and is connected with the fuse. When the integratedcircuit chip is tested, the latch-up effect is triggered, so the current in the latch-up circuit is continuously increased till the fuse is burnt out, and fusing of the fuse during testing is realized; when a plurality of fuses are tested, only the latch circuit of each fuse needs to be triggered in sequence, so test efficiency is improved, and the test time is saved.

Description

technical field [0001] The present disclosure relates to the technical field of integrated circuits, in particular, to a method for testing integrated circuit chips and fuses. Background technique [0002] With the development and progress of technology, integrated circuits are used more and more widely, and a large number of fuses are often included in integrated circuits. [0003] At present, the fuses used in integrated circuits are usually gate oxide fuses, which are in an open state before fusing, and require a large voltage difference between the conductive gate and the heavily doped layer when fusing , to blow the fuse. [0004] When performing integrated circuit testing, it is necessary to test the fuse, and the fusing efficiency of the gate oxide fuse is low, resulting in long test time and low test efficiency. [0005] It should be noted that the information disclosed in the above background section is only for enhancing the understanding of the background of the...

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present disclosure is to provide a method for testing integrated circuit chips and fuses, and then at least to a certain extent overcome the problems of long integrated circuit testing time and low testing efficiency caused by the limitations and defects of related technologies

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