Method for realizing interrupt response by using BMC on Feiteng platform

A platform and external interrupt technology, applied to the architecture with a single central processing unit, general-purpose stored program computers, instruments, etc., can solve problems such as CPU performance bottlenecks, and achieve the effect of simple implementation

Pending Publication Date: 2020-03-17
SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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Problems solved by technology

[0004] Aiming at the problems of the prior art, the present invention provides a method of using BMC to realize interrupt response on the Feiteng platform, realizes interrupt response through the cooperation of CPU and BMC, solves the problem that the polling method is easy to produce cpu performance bottleneck, and has the advantages of simple and convenient implementation Features

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  • Method for realizing interrupt response by using BMC on Feiteng platform
  • Method for realizing interrupt response by using BMC on Feiteng platform

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Embodiment Construction

[0023] The present invention provides a method for implementing interrupt response using BMC on the Feiteng platform:

[0024] The Feiteng platform CPU and BMC establish communication through CPLD. The BMC configures the GPIO pins as interrupt pins. The interrupt pins monitor external interrupt signals, and send the interrupt signals and corresponding interrupt conditions to the Feiteng platform CPU through the BMC.

[0025] The interrupt pins perform corresponding interrupt response control operations according to the default processing command or the interrupt processing command issued by the Feiteng platform CPU.

[0026] At the same time, a Feiteng platform that uses BMC to implement interrupt response corresponding to the above is provided. The Feiteng platform CPU and BMC establish communication through CPLD, and the BMC configures GPIO pins as interrupt pins. Send the interrupt signal and the corresponding interrupt situation to the Feiteng platform CPU,

[0027] The i...

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Abstract

The invention discloses a method for realizing interrupt response by using a BMC on a Feiteng platform, and relates to the technical field of computer signal response. The method includes adopting a CPLD to establish communication between a Feiteng platform CPU and a BMC; configuring a GPIO pin in a BMC as an interrupt pin, monitoring an external interrupt signal by using the interrupt pin, sending the interrupt signal and a corresponding interrupt condition to the Feiteng platform CPU through the BMC, and performing a corresponding interrupt response control operation according to the interrupt processing command. By using the method provided by the invention, the interrupt response is completed on the Feiteng platform through the cooperation of the CPU and the BMC; the problem that theCPU performance bottleneck is easily generated due to the fact that the Feiteng platform can only carry out interrupt response through a polling method is solved, and meanwhile the technical scheme has the advantages of being easy and convenient to implement and the like and is suitable for being applied and popularized on the Feiteng platform or other similar platforms.

Description

technical field [0001] The invention discloses a method for realizing interrupt response by using a BMC on a Feiteng platform, and relates to the technical field of computer signal response. Background technique [0002] In the system, interrupts are divided into external interrupts and internal interrupts. For external interrupts, the interrupt request signal is generated by an external device and applied to the NMI or INTR pin of the CPU. The CPU recognizes whether an interrupt request occurs by continuously detecting the NMI and INTR pin signals; for internal interrupts, the interrupt request The method does not need to be stimulated by an external signal, but is called by the internal interrupt control logic. When a certain interrupt source requires the CPU to perform interrupt service for it, an interrupt request signal is output to set the interrupt request trigger of the interrupt control system and request an interrupt to the CPU. The system requires the interrupt ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78
CPCG06F15/7817
Inventor 沈忱何孟宁刘月
Owner SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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