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Compatible aging test method and chip thereof

A aging test, chip technology, applied in the direction of electronic circuit test, environment/reliability test, components of electrical measuring instruments, etc., to achieve the effect of low cost

Active Publication Date: 2020-03-27
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this special mode cannot be entered due to the above-mentioned reasons of the aging test machine, so it is impossible to enter the special mode for switching

Method used

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  • Compatible aging test method and chip thereof
  • Compatible aging test method and chip thereof
  • Compatible aging test method and chip thereof

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Embodiment Construction

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. The components of the embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without cre...

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Abstract

The invention provides a compatible aging test method and a chip, and the method comprises the steps: enabling the chip to use the state of a low-speed receiving module before the low-speed test is not completed; and after the low-speed test is completed, the chip is set to be in the state of the high-speed receiving module. The chip comprises an adjustable receiving unit and a chip internal unit.The adjustable receiving unit comprises an adjusting module and a receiving module; the adjusting module is used for controlling the state of the receiving module to be a low-speed state or a high-speed state; and the receiving module comprises a transmission interface used for receiving signals. A signal of the aging test machine is received during the aging test, and signals of an external circuit are received during normal operation. And for a high-speed chip, the requirement of aging test of a low-speed working signal can be met, and the requirement of a high-speed signal during normal working can also be met.

Description

technical field [0001] The invention relates to the field of semiconductor chip testing. In particular, it relates to a compatible aging test method and a chip thereof. Background technique [0002] The durability aging test (BI Burn In) such as the reliability test of the semiconductor chip in the prior art adopts a basic functional test, that is, the operating frequency of the chip will be reduced below a lower frequency. This is due to cost control, the output driving ability of the burn-in test machine is weak, and the speed is low, which causes the signal input from the burn-in test machine to the product under test to rise and fall slowly, and the signal noise (noise) is extremely large. [0003] When the burn-in test machine (equipment) is performing the burn-in test (BI) of some products, especially for the test of high-speed chips, due to the high sensitivity of the receiver module (receiver) of these high-speed chips, because the burn-in test machine input The ri...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R1/04
CPCG01R31/28G01R31/003G01R1/0416
Inventor 俞冰谈杰王嵩
Owner XI AN UNIIC SEMICON CO LTD