Non-regular set associative cache group address mapping method

Abstract

The present invention relates to the field of storage technology, and discloses a non-regular set associative cache group address mapping method, comprising: determining the number of cache groups R, expressed as G0, G1..., GR-1, wherein the number of cache groups is not 2 Integral power; the capacity of the main memory is Q blocks, and the main memory is divided into g groups. When Q can be divisible by R, the number of blocks in each group of the main memory is equal to the number of groups of the cache, and the The blocks in the group are renumbered, respectively represented as b0, b1, ... bR-1; when Q cannot be divisible by R, the number of blocks in the group g-1 in the main memory group is equal to the number of groups in the cache, and these groups The blocks in the group are renumbered, respectively represented as b0, b1, ... bR-1, the number of blocks in the other group is equal to the remainder of dividing Q by R, and the blocks in the group are numbered b0, b1, ... bREM (Q / R )‑1; the main memory and the cache are mapped, and the blocks in each group in the main memory are copied to the group with the same number. Adopting the method in the present invention will greatly reduce the probability of continuously accessing the same group in the cache or excessively using the same group in the program.

Description

technical field [0001] The invention relates to the field of storage technology, in particular to an address mapping method of an irregular set associative cache group. Background technique [0002] Cache memory (cache) is the memory that exists between the main memory and the central processing unit (CPU). The computing speed of the CPU is much faster than the reading and writing speed of the main memory, which makes the CPU spend a long waiting time when accessing the memory, resulting in a decline in the overall performance of the system. In order to make up for the running speed gap between the CPU and memory in computer systems, modern CPUs generally use on-chip caches to cache commonly used memory data. The cache stores the data used by the CPU and its calculation results, allowing the CPU to access them first when processing next time. cache, if there is no data available to access the memory, so to improve the speed of operation. [0003] The mapping method refers ...

AI Technical Summary

Problems solved by technology

Since in the group associative method, the group address adopts the direct mapping method, an address in the memory can only be mapped to a unique group. Although the group adopts the full associative method, when multiple addresses are mapped to the same When in the group, the occurrence of group conflicts will still have a large impact on performance

This is mainly due to the following two reasons: (1) The number of cache lines in the group is limited. When the number of data lines to be loaded into this group exceeds the number of cache lines in the group, the replacement of cache lines will occur. That is, the cache line originally saved in the cache will be replaced by the newly loaded cache line. If the CPU wants to use the replaced cache line later, the cache will be missing, and it needs to be reloaded from the memory; (2) When a certain group of cache executes During the operation, in order to maintain the atomicity of the operation, other operations are not allowed on the group. Otherwise, if the replacement algorithm cannot select two replacement ways, the two operations next to each other may load the same way in the cache. One path was overwritten after loading causing functional bugs and performance issues

It can be seen that although the cache whose number of groups is an integral power of 2 is simple to implement, since the data structure specifications in computer programs are often also an integral power of 2, when the data structure scale is large or the number is large, it will be frequently cached. Group conflicts occur frequently, resulting in frequent replacement of cache items or blocking of cache access, resulting in a decrease in CPU performance

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