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DDR arbitration controller, video cache device and video processing system

An arbitration controller and arbiter technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of untimely response to high-bandwidth requirements, and achieve the effects of improving development efficiency and reducing development difficulty and time

Inactive Publication Date: 2020-05-12
SHENZHEN AOTO ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] Based on this, it is necessary to provide a DDR arbitration controller, a video cache device and a video processing system for the problem that the existing DDR memory arbitrator does not respond in time to high bandwidth requirements

Method used

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  • DDR arbitration controller, video cache device and video processing system
  • DDR arbitration controller, video cache device and video processing system
  • DDR arbitration controller, video cache device and video processing system

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Embodiment Construction

[0030] In order to more clearly understand the above objects, features and advantages of the present application, the present application will be described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terminology used herein in the description of the application is only for the purpose of describing specific embodiments, and is not intended to limit the application.

[0032] Such as figure 1 and image 3 As shown, an embodiment of the present application provides a DDR arbitration controller 10 for scheduling management of multi-channel users reading and writin...

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Abstract

The invention relates to a DDR arbitration controller, a video cache device and a video processing system. The DDR arbitration controller comprises an arbiter and a plurality of user channels. The user channel provides a read-write request; the arbiter is of a tree structure composed of a plurality of template arbitration nodes; the template arbitration node adopts a polling mechanism; wherein thedepth from at least one leaf node to the root node is smaller than the depths from other leaf nodes to the root node; and according to the number of the input ends of the template arbitration nodes on the path from the leaf node to the root node corresponding to each port, a time slice of accessing the DDR memory by the read-write request received by the port is determined. The tree structure isconstructed by utilizing template arbitration nodes, and different leaf nodes can be configured with different weights, so that user channels with high bandwidth requirements can be responded in time;and in response to different scenes, the circuit structure and codes of the template arbitration node can be reused, so that the development difficulty and time are reduced.

Description

technical field [0001] The invention relates to the field of memory control, in particular to a DDR arbitration controller, a video cache device and a video processing system. Background technique [0002] With the continuous development of video image technology, the resolution and frame rate of video are getting higher and higher, which puts forward very high requirements on the transmission bandwidth and processing performance of the video processing system. Currently, video buffering is an integral part of a video processing system. The cache components that are more frequently used now are mainly DDR SDRAM (Double Rate Synchronous Dynamic Random Access Memory, referred to as DDR memory). [0003] The video processing system also often involves processing operations such as collecting and playing multiple channels of video at the same time, so it is necessary to simultaneously cache and process multiple channels of video. Due to the limited transmission bandwidth of th...

Claims

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Application Information

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IPC IPC(8): G06F13/16
CPCG06F13/1605
Inventor 袁鸿声孙兴红吴振志吴涵渠
Owner SHENZHEN AOTO ELECTRONICS
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