APB bridge for realizing synchronous mode, APB bridge for realizing asynchronous mode and control method thereof

Abstract

The invention provides an APB bridge for realizing a synchronous mode, an APB bridge for realizing an asynchronous mode and a control method thereof. The APB bridge in the synchronization mode is provided with an AHB cache region, the APB cache region and the corresponding control logic, the situation that sampling errors occur when APB samples an AHB clock domain in the pre-simulation process oftraditional design is effectively avoided in the synchronization mode, and the adaptability of the APB bridge is improved. Asynchronous prefetching FIFO (First In First Out) by the APB bridge is set for realizing an asynchronous mode; a write command and write data transmitted by an APB bridge are transmitted through an asynchronous prefetching FIFO, the asynchronous prefetching FIFO independentlystores and outputs the data in the data according to different clocks, and the write command and the write data are transmitted to an APB bus end from an AHB bus end. Compared with the prior art, a new netlist does not need to be manually modified, synchronous or asynchronous transmission of data is achieved through control logic in the APB bridge, conversion of control signals and data from a wide bus AHB to a narrow bus APB is achieved, the code reuse rate can be increased, and the SOC design process is accelerated.

Description

technical field [0001] The present disclosure relates to the related technical field of APB bridges, and in particular, relates to an APB bridge realizing a synchronous mode, an APB bridge realizing an asynchronous mode and a control method thereof. Background technique [0002] The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art. [0003] In the AMBA (Advanced Microcontroller Bus Architecture, translated as Advanced Microcontroller Bus Architecture) on-chip bus protocol specification, the APB bridge is an important hub connecting the AHB high-speed bus and the APB bus, and plays a role in the data transmission between the master device and the peripheral device. Crucial role. The APB bridge is the only master device on the APB bus, and it is also one of the many slave devices on the AHB bus. The APB bridge meets the AHB and APB interface protocols, and it provides a command / dat...

AI Technical Summary

Problems solved by technology

[0005] In the traditional design scheme: in the synchronous mode of AHB clock and APB clock, when the frequency is multiplied, the AHB clock and APB clock generally use a dedicated timing synchronization interface signal (clk_en) to synchronize the interface timing. Multiple simulations have found that the AHB clock and the APB clock The APB clock is in the pre-simulation, that is, during the pre-simulation simulation, such as figure 1 As shown, because the balance adjustment of the clock tree is not made, it will cause the phase offset problem between the AHB clock (hclk in the figure) and the APB clock (pclk in the figure) and clk_en. The phase of the clock pclk in the figure is backward compared to the clock hclk Offset, the phase of clk_en is also shifted backward relative to hclk, the offset of pclk and clk_en cannot be clearly determined in the pre-simulation of the previous simulation

That is, when the AHB address haddr is sampled by the APB clock when clk_en is high, the phase relationship between the APB and the AHB clock is difficult to determine in the pre-simulation stage, and the APB may have a relatively large offset relative to the AHB clock, resulting in the sampled AHB The bus address (haddr) is the data after the change, then a sampling error will occur

For this kind of problem, it is necessary to manually add a delay solution to the synthesized netlist every time. This method needs to manually modify the new synthesized netlist every time, which is too cumbersome and error-prone

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