Camera Link data receiving system and Camera Link data transmission method based on an FPGA
A technology for receiving systems and data, applied in the field of data transmission, can solve problems such as the increase in the number of interface chips and the number of input and output interfaces, the limited transmission video data rate, and the unfavorable effective use of system resources, etc., to achieve the goal of reducing the number of input and output pins Effect
Inactive Publication Date: 2020-05-22
LUOYANG INST OF ELECTRO OPTICAL EQUIP OF AVIC
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[0003] At present, the main solution for Camera Link data reception is to use a special receiving chip to convert Camera Link data from LVDS format to parallel format data. This method is more complicated to design, and the transmission video data rate is easily limited by the Camera Link interface chip. , when it is necessary to transmit multiple channels of video in an airborne environment, the number of interface chips and the number of input and output interfaces required will increase exponentially, which is not conducive to the effective use of system resources
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[0014] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.
[0015] The schematic diagram of the invention is shown in figure 1 . It can be seen from the figure that the present invention mainly includes 6 units, a clock module, a data analysis module 0, a data analysis module 1, a data analysis module 2, a data analysis module 3, and a sequence adjustment module. The clock module implements the clock analysis function, and outputs the pixel clock and the deserialization clock. The 4 sets of data analysis modules respectively implement the 1:7 deserialization of the 4 sets of data, and each outputs a set of 7-bit data. The 4 sets of data signals pass through the bit sequence adjustment module to output 28-bit data signals, which are combined with the pixel clock to finally output the clock data signal of the Camera Link standard source.
[0016] An FPGA-based Camera Link data receiving system, the signal receiv...
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The invention provides a Camera Link data receiving system and a Camera Link data transmission method based on an FPGA. Signals received by the FPGA end are divided into five paths, wherein one channel is a clock signal, the other four paths are data signals with seven times of clock rate. Differential to single-ended conversion of a clock signal is realized. Through phase-locked loop, the clock signals are divided into pixel clocks and deserializing clocks. Pixel clock directly outputs, the frequency value of the deserialized clock is seven times of that of the input clock. In each differential data channel, differential to single-ended conversion of differential data is firstly completed to output a single-ended signal, the phase is adjusted according to a phase adjustment value output by a calibration and bit segmentation state machine, serial-parallel conversion of the data is realized in a deserializer according to a bit segmentation signal, and a clock and a data signal with thesame format of a Camera Link source end are output after bit sequence adjustment. According to the invention, the number of input and output pins for Camera Link data transmission is effectively reduced, the Camera Link standard bandwidth is effectively utilized, and the maximum rate supported by the Camera Link standard can be supported.
Description
technical field [0001] The invention relates to the field of data transmission, in particular to a receiving method for airborne video data transmission. Background technique [0002] Camera Link is a communication protocol specially designed for high-speed image and video data transmission, which uses low-voltage differential signal LVDS for transmission. One Camera Link includes 5 pairs of differential signals. The sending end converts 28-bit data signals and 1 clock signal into 5 pairs of differential signals at a ratio of 1:7. The receiving end converts 5 pairs of differential signals according to the Camera Link deserialization chip. into a 28-bit data signal and a clock signal. [0003] At present, the main solution for Camera Link data reception is to use a special receiving chip to convert Camera Link data from LVDS format to parallel format data. This method is more complicated to design, and the transmission video data rate is easily limited by the Camera Link int...
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Login to View More IPC IPC(8): H04N7/01H04N7/18
CPCH04N7/01H04N7/18
Inventor 张三刚祁超
Owner LUOYANG INST OF ELECTRO OPTICAL EQUIP OF AVIC