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Instruction correlation verification method and device, electronic equipment and storage medium

A technology of electronic equipment and verification methods, which is applied in the fields of electrical digital data processing, instrumentation, and calculation, and can solve the problems of low guidance value and insufficient knowledge of various situations of graphics processor instructions.

Active Publication Date: 2020-05-29
西安翔腾微电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the inventors have found that the result of instruction dependency verification obtained in the related art is not enough to fully understand various situations related to instructions that are likely to occur in the graphics processor, so that the result of instruction dependency verification is very important for avoiding instruction Associated situations have low instructional value

Method used

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  • Instruction correlation verification method and device, electronic equipment and storage medium
  • Instruction correlation verification method and device, electronic equipment and storage medium
  • Instruction correlation verification method and device, electronic equipment and storage medium

Examples

Experimental program
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Embodiment 1

[0063] See figure 1 , figure 1 It is a schematic flowchart of a method for verifying the relevance of instructions provided by an embodiment of the present invention, and the method may include the following steps:

[0064] Step S101: Execute a plurality of preset first verification programs respectively to obtain a first verification result.

[0065] Wherein, any first verification program is composed of one or more stimulus test programs selected from a plurality of preset stimulus test programs; each stimulus test program includes a set of data-related, structure-related or control-related instructions, And the total number of instructions contained in the stimulus test program constituting any first verification program is not greater than the number of instruction issuance indicated by the size of the instruction issuance window of the graphics processor.

[0066] It can be understood that, for each first verification program, if the first verification program consists ...

Embodiment 2

[0089] In order to clarify the scheme, the construction method of multiple preset first verification programs, multiple second verification programs, and multiple third verification programs will be exemplarily described below. like image 3 As shown, the construction method may include the following steps:

[0090] Step S301: Obtain various kinds of reference information.

[0091] Among them, the various reference information may include: the register read and write path of the graphics processor, the types of each instruction execution unit included in the graphics processor, the number of each type of instruction execution unit, and the processing pipeline of each type of instruction execution unit structure, the instruction execution cycle of each type of instruction execution unit, and the read and write operation types of each type of instruction execution unit read and write instructions.

[0092] In this step, there are many specific implementation manners for acquir...

Embodiment 3

[0142] Corresponding to the above instruction dependency verification method, an embodiment of the present invention also provides an instruction dependency verification device, such as Image 6 As shown, the device may include:

[0143] The first execution module 601 is configured to respectively execute a plurality of preset first verification programs to obtain a first verification result; wherein, any one of the first verification programs is selected from a plurality of preset stimulus test programs or a plurality of stimulus test programs; each of the stimulus test programs includes a set of data-related, structure-related or control-related instructions, and the total number of instructions contained in the stimulus test programs that constitute any first verification program is not The number of instruction issuances indicated by the size of the instruction issuance window greater than the graphics processor;

[0144] The second execution module 602 is configured to r...

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PUM

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Abstract

The invention discloses an instruction correlation verification method and device, electronic equipment and a storage medium. The method comprises the following steps: respectively executing a plurality of first verification programs, a plurality of second verification programs and a plurality of third verification programs to obtain a verification result; wherein each of the first verification program and the second verification program is composed of one or more excitation test programs; wherein the third verification program is composed of a first verification program and a second verification program which are randomly selected; each excitation test program includes a set of data-related, structure-related, or control-related instructions, wherein the number of instructions contained in the first verification program is smaller than or equal to the size of an instruction transmitting window of the graphics processor; wherein the number of instructions contained in the second verification program is greater than the size of the instruction transmitting window; according to the method and the device, various conditions related to the instruction easily occurring in the graphic processor can be comprehensively known, so that the guidance value of the correlation verification result of the instruction for avoiding the conditions related to the instruction can be improved.

Description

technical field [0001] The invention belongs to the field of computer graphics, and in particular relates to an instruction correlation verification method, device, electronic equipment and storage medium. Background technique [0002] In the field of computer graphics, whether the instructions run in the graphics processor are related or not is an important factor affecting the execution efficiency and execution accuracy of the program. Here, instruction correlation includes data correlation, structure correlation and control correlation. Among them, the command correlation refers to the data correlation involved in running the command; the structural correlation refers to the hardware structure resource correlation required to run the command; the control correlation refers to the pipeline processing process correlation of the command. In order to improve the execution efficiency and execution accuracy of the program, it is necessary to perform instruction-related verific...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36
CPCG06F11/3688Y02D10/00
Inventor 苏东阁孙成璐杨寒雪刘红红纪楠薛凌艺
Owner 西安翔腾微电子科技有限公司
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