a flash memory

Abstract

A flash memory, comprising a bidirectional I / O interface (10), a processing unit (20) and a storage unit (30); the processing unit (20) is electrically connected to the bidirectional I / O interface (10) and the storage unit (30) respectively The processing unit (20) is used to obtain the stored data output by the storage unit (30) at the rising edge of the clock signal (SCK), obtain the first group of output data, and send the first group of output data to the two-way The I / O interface (10) is output by the bidirectional I / O interface (10); at the falling edge of the clock signal (SCK), the stored data output by the storage unit (30) is obtained and shift operation processing is carried out to obtain the first Two sets of output data, and sending the second set of output data to the bidirectional I / O interface (10) for output by the bidirectional I / O interface (10). The flash memory of the invention is novel in design and strong in practicability.

Description

technical field [0001] The invention relates to the field of circuits, in particular to a flash memory. Background technique [0002] Serial interface flash memory is a commonly used data storage component, but all operations such as instructions, addresses, and data are serially input and output, resulting in slow data transfer rates, especially during read operations. [0003] In order to improve the data transmission rate, the existing technology usually improves the frequency of the transmission clock and multi-pin multiplexing. The former scheme is specifically: use the internal high-speed clock to sample the rising and falling edges of the external transmission clock respectively. , and use it as an internal clock signal or control signal to transmit data to achieve twice the transmission rate of the external transmission clock; the latter scheme is that the multi-pin multiplexing mechanism is similar to the parallel transmission of multiple lines, which can achieve T...

AI Technical Summary

Problems solved by technology

The disadvantage of the above two schemes is that due to the existence of the internal high-speed clock, the external clock has an upper limit problem. Generally, when the frequency of the external clock is greater than a quarter of the internal high-speed clock, the internal clock signal or control signal will not be generated stably. , resulting in the inability to transmit data, and due to the existence of the internal high-speed clock, the power consumption will be large

However, multi-pin multiplexing may not be usable in certain states.

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