Alexnet forward network accelerator based on FPGA (Field Programmable Gate Array)

A network accelerator and accelerator technology, applied in the direction of biological neural network model, neural architecture, physical realization, etc., can solve the problems of computer hardware resource consumption, Alexnet model large convolution calculation and memory access operation, etc., to achieve reduced content, reduced The effect of small consumption and reduction of redundant data

Pending Publication Date: 2020-06-26
YUNNAN UNIV
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Problems solved by technology

[0004] The purpose of the invention of the present invention is: for the above-mentioned existing problems, provide a kind of Alexnet forward network accelerator based on FPGA; The present inventio

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  • Alexnet forward network accelerator based on FPGA (Field Programmable Gate Array)
  • Alexnet forward network accelerator based on FPGA (Field Programmable Gate Array)
  • Alexnet forward network accelerator based on FPGA (Field Programmable Gate Array)

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Embodiment 1

[0027] An FPGA-based Alexnet forward network accelerator, such as figure 1 As shown, it includes: processor 1, external memory 5, buffer 4, controller 6, AX14-Lite bus module 2 and AX14 bus module 3; said AX14-Lite bus module 2 and AX14 bus module 3 are connected with the processor respectively 1 connection; the external memory 5, the buffer 4 and the processor 1 are respectively connected to the AX14 bus module 3.

[0028] Described external memory 5 is used for storing accelerator operation or calculation data; In the present embodiment, external memory 5 is DDR3, can realize high-speed operation, and can reduce power consumption; External memory 5 can preserve the various data that accelerator calculates, so that Call anytime.

[0029] The buffer 4 is used to store the intermediate results of the accelerator calculation; in this embodiment, the buffer 4 is a double RAM buffer 4, which is mainly used to temporarily store the temporary calculation results of the accelerator ...

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Abstract

The invention discloses an Alexnet forward network accelerator based on an FPGA. The Alexnet forward network accelerator comprises a processor, an external memory, a buffer, a controller, an AX14-Litebus module and an AX14 bus module, wherein the AX14-Lite bus module and the AX14 bus module are respectively connected with the processor; the external memory, the buffer and the processor are respectively connected with the AX14 bus module; the external memory is used for storing accelerator operation or calculation data; the buffer is used for storing an intermediate result calculated by the accelerator; the controller is used for controlling starting, calculation and time measurement of the accelerator; the AX14-Lite bus module is used for transmitting an instruction; the AX14 bus module is used for data transmission; the processor is used for realizing acceleration. According to the invention, redundant data generated by the Alexnet accelerator during operation is reduced, the contentof convolution calculation and memory access operation is reduced, and the consumption of computer hardware resources is also reduced.

Description

technical field [0001] The invention relates to the field of neural network accelerators, in particular to an FPGA-based Alexnet forward network accelerator. Background technique [0002] The Alexnet network model was proposed by Alex and won the first prize in the ImageNet2012 image classification competition. It is a classic model of CNN in image classification applications. The first five layers of Alexnet are convolutional layers, and the last three layers are fully connected layers. The model receives 3 images with dimensions (224, 224) as input, and after a series of convolution calculations and pooling operations, it finally outputs a 1000-dimensional vector, representing a classifier containing 1000 classification labels; volume The accumulation layer is composed of a certain number of feature maps, and its function is to extract the features of the input image. There are a large number of convolutional calculations in the convolutional layer, accounting for more t...

Claims

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Application Information

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IPC IPC(8): G06N3/063G06N3/04
CPCG06N3/063G06N3/045
Inventor 杨军田粉仙李娟孙欣欣李克丽梁颖
Owner YUNNAN UNIV
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