A kind of nand memory and its manufacturing method

Abstract

The invention relates to a NAND memory and a manufacturing method thereof. The NAND memory comprises: a substrate; a laminated structure located above the substrate, and the laminated structure includes epitaxial epitaxial structures sequentially arranged above the substrate in a vertical direction perpendicular to the substrate. layer, the bottom selection gate structure layer and the storage array stack, the storage array stack includes gate layers and interlayer insulation layers alternately stacked up and down; most of the gate line slits run through the stack structure; at the level parallel to the substrate In the lateral direction, the channel storage structure located between the gate line slits; between the lower end of the gate line slit in the horizontal longitudinal direction and the substrate, separating the epitaxial layer from the lower end of the gate line slit spacer; and a flat layer covering the spacer, so that when the gate line slit is formed by an etching process, it is not necessary to precisely control the lower end of the gate line slit to terminate at the boundary of the epitaxial layer, which can reduce the impact on the etching process. The accuracy requirements of the process, thereby reducing the cost of etching equipment and increasing product reliability.

Description

【Technical field】 [0001] The invention relates to the technical field of memory, in particular to a NAND memory and a manufacturing method thereof. 【Background technique】 [0002] As technology develops, the semiconductor industry is constantly looking for new production methods to allow each memory die in a memory device to have a greater number of memory cells. Among them, 3D NAND (three-dimensional NAND) memory has become a cutting-edge three-dimensional memory technology with great development potential due to its advantages of high storage density and low cost. [0003] The existing 3D NAND memory includes a substrate, an epitaxial layer sequentially disposed on the substrate, a bottom selection gate and a stack structure, and a gate line slit disposed in the stack structure and passing through the bottom selection gate to the epitaxial layer. However, in the manufacturing process of 3D NAND memory, in order to ensure the yield and reliability of the memory device, whe...

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Problems solved by technology

However, in the manufacturing process of 3D NAND memory, in order to ensure the yield and reliability of the memory device, when the above-mentioned gate line slit is formed by an etching process, it is necessary to precisely control the lower end of the gate line slit to terminate in the epitaxial layer. At the border, there are problems of high precision requirements for the etching process and high cost of etching equipment

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