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Method for forming bump-on-trace (BOT) assembly and semiconductor structure

A technology of bumps and traces on traces, used in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components and other directions

Active Publication Date: 2020-07-10
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Unfortunately, reducing the spacing between adjacent metal traces can lead to undesired or adverse effects

Method used

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  • Method for forming bump-on-trace (BOT) assembly and semiconductor structure
  • Method for forming bump-on-trace (BOT) assembly and semiconductor structure
  • Method for forming bump-on-trace (BOT) assembly and semiconductor structure

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Embodiment Construction

[0037] The making and using of various embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0038] The invention will be described with respect to an embodiment in a specific context, namely a package incorporating bump-on-trace (BOT) interconnects. However, the concepts in the present invention may also be applied to other packages, interconnect assemblies or semiconductor structures.

[0039] common reference Figure 1 to Figure 3 , shows a bump-on-trace (BOT) assembly 10 for a package 12 . As will be explained more fully below, BOT assembly 10 provides additional benefits and advantages over BOT assemblies formed using other methods. For example, t...

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PUM

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Abstract

Embodiments of the invention provide a method of forming a bump-on-trace (BOT) of a package and a semiconductor structure. The method comprises the following steps: forming a bonding trace on the substrate, wherein in the plane view, the bonding trace has a first portion, a second portion, and a third part connecting the first part to the second portion, the first side wall of the first part and the first side wall of the second part are collinear, the second side wall of the first part is collinear with the second side wall of the second part and the second side wall of the third portion, inthe plan view, the first side wall of the third part has one or more first grooves recessed toward the second side wall of the third portion, and the second side wall of the third part is integrally aflat side wall; disposing a conductive pillar over the third part of the bonding trace such that the conductive pillar at least partially covers one or more first grooves in the third part of the bonding trace; and electrically connecting the bonding trace to the conductive pillar.

Description

[0001] divisional application [0002] This application is a divisional application with the title "Trace Design for Bump-on-Trace (BOT) Components" and patent application number 201410431316.6 filed on August 28, 2014. technical field [0003] The present invention relates to the field of semiconductors, and more particularly, to trace design for bump-on-trace (BOT) assemblies. Background technique [0004] In a package such as a flip chip chip scale package (fcCSP), an integrated circuit (IC) or die is mounted to a substrate (e.g., a printed circuit board (PCB) ) or other integrated circuit carrier). BOT interconnects employ solder to electrically connect the bumps of the IC to the traces of the substrate. [0005] In accordance with the requirements of smaller packages, attempts are often made to reduce the distance between adjacent bumps, also known as the bump pitch. One way to reduce the bump pitch is by reducing the distance between adjacent metal traces. [0006]...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60
CPCH01L24/16H01L24/81H01L2224/16225H01L2224/81815H01L2924/12042H01L2924/14H01L2224/10175H01L23/49811H01L24/13H01L2224/13013H01L2224/13014H01L2224/13023H01L2224/131H01L2224/13147H01L2224/13294H01L2224/133H01L2224/16013H01L2224/16238H01L2224/81385H01L2224/81447H01L2924/381H01L2924/3841H05K2203/1173H05K3/3436H05K2201/10674H01L2224/16227H01L2224/8112H01L2224/16105Y02P70/50H01L2924/00H01L2924/00014H01L2924/014H01L24/05H01L2224/05552H01L2224/05011H01L2224/05012H01L2224/0401H01L2224/05551H01L2224/08053H01L2224/0807H01L2224/16012H01L2224/16113H01L24/11
Inventor 林彦良陈承先郭庭豪
Owner TAIWAN SEMICON MFG CO LTD