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Capacitive semiconductor element

A semiconductor and capacitive technology, applied in the field of capacitive semiconductor components, can solve problems such as grounding interference, and achieve the effect of reducing the impact of interference

Active Publication Date: 2020-07-17
NEXCHIP SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there are cases where a parasitic capacitance is generated between the wiring region of the MOM and the well region in the silicon substrate
When parasitic capacitance occurs, there is a possibility of interference influence from the ground (GND), such as interference influence introduced from the P-type well connected to the GND line
That is, the MOM circuit is susceptible to interference

Method used

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no. 1 Embodiment approach

[0065] Hereinafter, a first embodiment of the capacitive semiconductor element according to the present invention will be described with reference to the drawings.

[0066] figure 1 It is a cross-sectional view of the capacitive semiconductor element 1 according to the first embodiment of the present invention. Such as figure 1 As shown, the capacitive semiconductor element 1 according to the present embodiment includes a wiring region LA and a silicon substrate Sub on which the wiring region LA is laminated. The wiring region LA refers to a region that is laminated on the silicon substrate Sub to form capacitive elements, wiring, and the like.

[0067] A capacitive region (capacitive element) CR is formed in the wiring region LA, and the capacitive region CR can be formed by utilizing a thin film capacitance. For example, in the wiring area LA, Metal-Oxide-Metal (MOM) capacitors or Metal-Insulator-Metal (MIM) capacitors are formed. In addition, as long as it is a capaciti...

no. 2 Embodiment approach

[0092] Next, a capacitive semiconductor element according to a second embodiment of the present invention will be described.

[0093] In this embodiment, the case of suppressing parasitic capacitance will be further described. Hereinafter, the capacitive semiconductor element according to this embodiment will be mainly described in terms of points different from those of the first embodiment.

[0094] Figure 7 It is a cross-sectional view of the capacitive semiconductor element 1 according to the present embodiment. Figure 7 and figure 1 Also taking the following case as an example: in the NMOS region (P-type well) where the NMOS is formed, each dummy device is arranged in the dummy device region DA below the capacitive region CR.

[0095] Such as Figure 7 As shown, a well region, an STI region, and a silicon region D are formed on the silicon substrate Sub. Further, an epitaxial region EX is formed on the silicon substrate Sub. The epitaxial region EX is formed betwe...

no. 3 Embodiment approach

[0125] Next, a capacitive semiconductor element according to a third embodiment of the present invention will be described.

[0126] In this embodiment, a case where the parasitic capacitance is further suppressed will be described. Hereinafter, the capacitive semiconductor element according to this embodiment will be mainly described on points different from those of the first embodiment and the second embodiment.

[0127] Figure 21 It is a cross-sectional view of the capacitive semiconductor element 1 according to the present embodiment. Figure 21 and figure 1 Also taking the following case as an example: in the NMOS region (P-type well) where the NMOS is formed, each dummy device is arranged in the dummy device region DA directly below the capacitive region CR.

[0128] Such as Figure 21 As shown, an STI region and a silicon region D are formed in the silicon substrate Sub. In addition, in the silicon substrate Sub, an epitaxial region EX is formed between the silic...

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Abstract

The purpose of the present invention is to provide a capacitive semiconductor element. A The capacitive semiconductor element (1) is provided with: a silicon substrate (Sub), and a wiring region (LA)laminated on the surface of the silicon substrate (Sub), wherein, the the wiring region (LA) having is provided with a capacitive region (CR), and the; a silicon substrate (Sub) includes: a well region (P-type well); an STI region which is formed on the surface of the silicon substrate (Sub) and is in contact with the well region (P-type well) and the wiring region (LA); and a silicon region (D) that which is formed on the surface of the silicon substrate (Sub) and, is in contact with the well region (P-type well) and the wiring region (LA) in a region other than the STI region, and includes an impurity having a polarity opposite to that of the well region (P-type well). According to the inventioncapacitive semiconductor element, the influence of interference on the capacitive region can be reduced.

Description

technical field [0001] The invention relates to a capacitive semiconductor element. Background technique [0002] In the field of integrated circuits, Metal-Oxide-Metal (MOM) (metal-oxide-metal) capacitors or Metal-Insulator-Metal (MIM) (metal-insulator-metal) capacitors have been used (for example, Patent Document 1: U.S. Patent No. 8198698 specification), which is formed by wiring capacitors. [0003] In order to improve the accuracy of the capacitance value of the wiring capacitance, for example, dummy device patterns are arranged on the silicon substrate under the MOM. For example, dummy device patterns are set on the surface of the substrate to meet the preset densities on the STI and well regions. However, there are cases where a parasitic capacitance is generated between the wiring region of the MOM and the well region in the silicon substrate. When a parasitic capacitance occurs, there is a possibility of interference influence from the ground (GND), for example, ...

Claims

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Application Information

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IPC IPC(8): H01L23/522H01L49/02
CPCH01L23/5223H01L28/40
Inventor 田矢真敏川村昌靖夏目秀隆藤井康博
Owner NEXCHIP SEMICON CO LTD