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Fast inter-core data synchronization method for multi-core parallel computing

A parallel computing and data synchronization technology, applied in computing, computer, electrical and digital data processing, etc., can solve the problems of slow operation speed, many computing resources, multiple clock cycles, etc., to improve efficiency, reduce clock cycles, and reduce operations. effect of times

Pending Publication Date: 2020-07-28
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

The problem is that because the data in the prefetcher and the data cache are discarded multiple times, and the data cache is written back multiple times, a lot of computing resources are consumed, that is, the multi-core parallel computing scheduling method itself occupies a large amount of time. More clock cycles, slower operation speed

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  • Fast inter-core data synchronization method for multi-core parallel computing
  • Fast inter-core data synchronization method for multi-core parallel computing
  • Fast inter-core data synchronization method for multi-core parallel computing

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Embodiment Construction

[0044] The present invention will be further described below in conjunction with specific embodiments. It should be understood that the following examples are only used to illustrate the present invention but not to limit the scope of the present invention.

[0045] Such as figure 1 Shown is the fast inter-core data synchronization method of the present invention, which is used to maintain inter-core data consistency during DSP multi-core parallel computing, and is suitable for DSPs, such as C66x series DSPs, which are based on the multi-core parallelism disclosed in the patent document CN 201811305984.9 The calculation scheduling method is improved, which includes the following steps:

[0046] Step S1: According to the inter-core connection relationship of the multi-core parallel computing model, configure buffers and buffer data structures between each two directly connected cores in the inter-core connection relationship, and set in each buffer data structure Buffer write...

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Abstract

The invention provides a fast inter-core data synchronization method for multi-core parallel computing, which comprises the following steps of: configuring a buffer area and a buffer area data structure between every two directly connected cores, and setting a buffer area write-in indicator and a buffer area read indicator in each buffer area data structure; initializing a buffer area writing indicator and a buffer area reading indicator; enabling all the cores to execute the steps of reading the inter-core data and writing the inter-core data at the same time; and repeating the steps of reading the inter-core data and writing the inter-core data. According to the method, the buffer area write-in indicator and the buffer area read indicator are configured at the same time, the frequency ofoperating the prefetcher and the data cache can be reduced, and therefore the efficiency of the multi-core parallel computing scheduling method is improved while correct transmission of data is guaranteed.

Description

technical field [0001] The invention belongs to the field of parallel computing, and in particular relates to a fast inter-core data synchronization method for multi-core parallel computing. Background technique [0002] DSP (Digital Signal Processor) has been widely used in image processing, consumer electronics, instrumentation, industrial control, automobile, medical treatment and other fields due to its powerful computing power. In order to improve performance, DSP often has multiple processor cores, such as the C66x series DSP of TI (Texas Instruments), which can be configured with up to 8 cores. In order to give full play to the performance of multi-core DSP, it is necessary to distribute computing tasks to multiple processor cores for parallel computing. The most popular DSP multi-core parallel computing method is TI's SYS / BIOS operating system. This operating system has done a lot of adaptation and packaging according to the hardware structure characteristics of DS...

Claims

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Application Information

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IPC IPC(8): G06F15/167G06F15/177
CPCG06F15/167G06F15/177Y02D10/00
Inventor 王旭陈南希张晓林
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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