A storage data access method and communication device

Abstract

The invention provides a storage data access method and a communication device, which uses a random access memory and realizes data interaction between a programmable logic device and a coprocessor. During the interaction process, the random access memory compares its first port And the operation request received by the second port allows the programmable logic device or the coprocessor to read / write the stored data in other different address areas at the same time when the signal of the address area requested by the two sides is different, so as to improve the communication efficiency.

Description

technical field [0001] The invention belongs to the technical field of nuclear power, and relates to a stored data access method and a communication device. Background technique [0002] In the development of digital instrument control system of nuclear power plant, FPGA technology is gaining more and more attention. FPGA technology is the abbreviation of "Field Programmable Logic Gate Array", which is a semiconductor device including programmable logic components, programmable interconnect lines and programmable I / O. The application of data interaction between FPGA and coprocessor is very extensive. For example, the development of field bus communication equipment or industrial communication protocol gateway in digital instrument control system requires coprocessors, such as ARM, DSP, microcontrollers and other microprocessors (MCU), Realize the field bus protocol stack, on the one hand, FPGA realizes the communication with the coprocessor MCU, on the other hand, realizes ...

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Problems solved by technology

[0004] In view of the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a storage data access method and a communication device, which are used to solve the problem of utilizing traditional semaphore interaction in the prior art, so that various operations of the interaction can only be performed on the FPGA side. The two sides of the MCU side are serially executed, resulting in the problem of low communication rate

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