Radar turntable north calibration control system
A control system and radar technology, applied in the field of radar, can solve the problems of redundancy and achieve the effect of reducing the delay effect
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0030] like Figure 1 to Figure 3 As shown, the radar turntable north correction control system of the present invention includes a position counter, a north correction module, a data communication module, a data storage module and an azimuth pulse output module that work in parallel in the FPGA; it also includes an external clock frequency multiplier module, The external clock frequency multiplier module is respectively connected with the position counter, the school north module, the data communication module, the data storage module and the azimuth pulse output module;
[0031] The external clock module continuously inputs clock frequency signals for the position counter, the school north module, the data communication module, the data storage module and the azimuth pulse output module;
[0032] The position counter module records the encoder signal input by the encoder according to the clock frequency signal, converts it into a position signal, and stores it in the data st...
Embodiment 2
[0036] On the basis of the above embodiment, in order to further implement the present invention better, the external clock frequency multiplication module uses an external active crystal oscillator as the clock source, and generates a global synchronous clock and generates an output through the FPGA internal phase-locked frequency multiplication module. Pulse clock. The invention needs to output the azimuth count pulse signal and the reset pulse signal, which are divided into TTL level and RS422 level. The signal of each level adopts backup redundancy processing, wherein the azimuth count pulse is 16384P / r, and the reset pulse is 1P / r r, the pulse width is 10±0.5μs, and the synchronization error between counting pulses is not greater than 50ns, and the synchronization error between reset pulses is not greater than 50ns. The FPGA chip uses an external active crystal oscillator as the clock source with a frequency of 50MHz. The global synchronization clock (50MHz) and the clock...
Embodiment 3
[0038] On the basis of the above embodiment, in order to further implement the present invention better, the position counter module collects the encoder signal for counting, the encoder is an incremental encoder, and the output signal is a square wave signal with a difference of 90° and a Zero signal. The encoder is an incremental encoder, and the output signal is the square wave signal A, B and the zero signal Z with a difference of 90°, such as figure 2 shown.
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More