D trigger structure with asynchronous setting reset and rapid output
A set-reset and flip-flop technology, applied in the direction of pulse generation, electrical components, and electric pulse generation, can solve problems affecting the loop speed of the analog-to-digital converter and limit the performance of the analog-to-digital converter, so as to reduce the difficulty of high-speed design , Reduce logic delay, low transmission delay effect
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[0026] Such as Figure 2-Figure 4 Shown: The structure of a fast output D flip-flop with asynchronous set reset of this embodiment includes a follower latch circuit, a transmission latch circuit, and a feedforward acceleration circuit;
[0027] The following latch circuit includes a first transmission gate T1, a sixth transmission gate T6, and a first NOT gate N1 that are coupled in sequence. A first feeder is connected in series with both ends of the first NOT gate N1, and the first feeder is sequentially coupled and connected to the fourth The transmission gate T4, the second conduction node, the second NOT gate N2 and the first PMOS transistor P1, the second conduction node is coupled to the drain of the third PMOS transistor P3 and the drain of the first NMOS transistor M1, the first The source and drain of the PMOS tube P1 are connected to the first feeder line;
[0028] The transmission latch circuit includes a seventh transmission gate T7, a second transmission gate T2, and...
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