[0026] Such as Figure 2-Figure 4 Shown: The structure of a fast output D flip-flop with asynchronous set reset of this embodiment includes a follower latch circuit, a transmission latch circuit, and a feedforward acceleration circuit;
[0027] The following latch circuit includes a first transmission gate T1, a sixth transmission gate T6, and a first NOT gate N1 that are coupled in sequence. A first feeder is connected in series with both ends of the first NOT gate N1, and the first feeder is sequentially coupled and connected to the fourth The transmission gate T4, the second conduction node, the second NOT gate N2 and the first PMOS transistor P1, the second conduction node is coupled to the drain of the third PMOS transistor P3 and the drain of the first NMOS transistor M1, the first The source and drain of the PMOS tube P1 are connected to the first feeder line;
[0028] The transmission latch circuit includes a seventh transmission gate T7, a second transmission gate T2, and a third NOT gate N3, which are sequentially coupled and connected. A second feeder line is connected in parallel at both ends of the third NOT gate N3, and the second feeder line is sequentially coupled and connected to the third The transmission gate T3, the first conduction node, the fourth NOT gate N4 and the second PMOS transistor P2, the first conduction node is coupled to the drain of the fourth PMOS transistor P4 and the drain of the second NMOS transistor M2, and the second The source and drain of the PMOS tube P2 are connected to the second feeder line;
[0029] The feedforward acceleration circuit includes a fifth non-gate N5, a third conduction node, and a fifth transmission gate T5 that are sequentially coupled and connected, the third conduction node and the drain of the fifth PMOS transistor P5 and the drain of the third NMOS transistor M3 connection;
[0030] The input terminal of the follower latch circuit is the input terminal of the first transmission gate T1, and the output terminal is the output terminal of the first NOT gate N1;
[0031] The input terminal of the transmission latch circuit is the input terminal of the seventh transmission gate T7, and the output terminal is the output section of the third NOT gate N3;
[0032] The input terminal of the feedforward acceleration circuit is the input terminal of the fifth NOT gate N5, and the output terminal is the output terminal of the fifth transmission gate T5;
[0033] The output terminal of the follower latch circuit is connected with the input terminal of the transmission latch circuit, the input terminal of the feedforward acceleration circuit is connected with the input terminal of the transmission latch circuit, and the output terminal of the feedforward acceleration circuit is connected with the output terminal of the transmission latch circuit ;
[0034] The reverse control terminal of the first transmission gate T1, the forward control terminal of the second transmission gate T2, the forward control terminal of the fifth transmission gate T5 and the gate of the second PMOS transistor P2 are connected to the first clock signal CKCK; The forward control terminal of the four transmission gate T4, the gate of the third PMOS transistor P3, the gate of the second NMOS transistor M2 and the gate of the third NMOS transistor M3 are connected to the forward reset signal RSTRST; the fourth transmission gate T4 The reverse control terminal, the gate of the first NMOS transistor M1 and the gate of the second PMOS transistor P2 are connected to the reverse setting signal SETB; the gate of the fifth PMOS transistor P5 is connected to the forward setting signal SET; sixth The reverse control end of the transmission gate T6, the reverse control end of the seventh transmission gate T7, and the reverse control end of the third transmission gate T3 are connected to the forward enable signal EN_SR; the forward control end of the sixth transmission gate T6, The forward control terminal of the seventh transmission gate T7 and the forward control terminal of the third transmission gate T3 are connected to the reverse enable signal ENB_SR.
[0035] Further in this embodiment, the forward control terminal of the first transmission gate T1, the gate of the first PMOS transistor P1, the reverse control terminal of the second transmission gate T2, and the reverse control terminal of the fifth transmission gate T5 are connected The second clock signal CKB, the second clock signal CKB is used as a reserved signal and can be used to supplement other functions, which will not be repeated here.
[0036] Further in this embodiment, a D flip-flop structure with asynchronous set reset and fast output in the present invention also includes a seventh invertor N7, an eighth invertor N8, a ninth invertor N9, and a first AND Not gate N6, the input end of the seventh NOT gate N7 is connected to the reverse reset signal RSTB and outputs the forward reset signal RST, and the input end of the eighth NOT gate N8 is connected to the reverse set signal SETB and outputs the forward set signal SET, the input terminal of the ninth NAND gate N9 is connected to the forward enable signal EN_SR and the reverse enable signal ENB_SR is output, and the two input terminals of the first NAND gate N6 are connected to the forward set signal SET and the forward reset signal RST and output positive enable signal EN_SR.
[0037] The specific principles of the present invention are as follows:
[0038] The new structure of the high-speed asynchronous set-reset D flip-flop in this design can be divided into three parts. The first stage consists of the first transmission gate T1, the sixth transmission gate T6, and the fourth transmission gate T4. The two NOT gate N2, the first PMOS tube P1, the third PMOS tube P3, and the first NMOS tube M1 constitute a follower latch circuit;
[0039] The second stage consists of a transmission gate, a seventh transmission gate T7, a second transmission gate T2, a third transmission gate T3, a third inverter N3, a fourth inverter N4, and a second PMOS transistor P2, a fourth PMOS transistor P4, and a fourth NMOS tube M4 tube constitutes a transmission latch circuit;
[0040] The third stage is a feedforward acceleration circuit composed of a fifth transmission gate T5, a fifth NOT gate M5, a fifth PMOS tube P5 and a third NMOS tube M3 tube;
[0041] In addition, there are seventh NOT gate N7, eighth NOT gate N8, and ninth NOT gate N9 for logic conversion, and NAND gate N6 for generating the enable signal EN_SR for controlling the transmission gate.
[0042] In the normal working mode that does not require setting and resetting, the setting signal SET and the reset signal RST are high, and the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3 and The first PMOS tube P1, the second PMOS tube P2, and the third PMOS tube P3 are all turned off and do not work. The third transmission gate T3, the sixth transmission gate T6, the transmission gate used to shield the input signal when resetting The seventh transmission gate T7 is fully turned on and has no effect, which is consistent with the principle of the traditional D flip-flop.
[0043] When the first clock signal CK is low, the first transmission gate T1 is turned on, and the input signal D passes through the first transmission gate T1 and the first NOT gate N1 to obtain the signal DB; P2 is turned off, and the second inverter in the first feeder The gate N2, the first PMOS transistor P1 does not work; the second transmission gate T2 is turned off, the second PMOS transistor P2 is turned on, the third inverter N3, the fourth inverter N4, and the third transmission gate T3 in the second feeder Turn on, play a latch function. When the rising edge of the clock signal arrives, the first transmission gate T1 is turned off, the second transmission gate T2 is turned on, and the first feeder is active, latching the information of D when the first clock signal CK is low in the previous moment; the second transmission The gate T2 is turned on, the second PMOS transistor P2 is turned off, and the DB signal is transmitted to the Q output through the third NOT gate N3. When the first clock signal CK is at a high level, the first transmission gate T1 is not turned on, and the state of Q will be consistent with the D signal latched by the rising edge.
[0044] The difference from the traditional structure is that when the first clock signal CK is at the rising edge, the signal DB passes through the fifth NOT gate N5 and the fifth transmission gate T5 in the feedforward circuit than the seventh transmission gate T7 and the first transmission gate T7 in the main signal path. The second transmission gate T2 and the third NOT gate N3 reach the Q terminal faster, which is equivalent to two parallel signal transmissions, which can achieve faster transmission speed.
[0045] If the D flip-flop needs to be set at a certain moment (make Q immediately high), then make the reverse set signal SETB low. At this time, the third transmission gate T3, the sixth transmission gate T6 and the seventh transmission gate T7 for shielding the input signal are all turned off. In the second-stage transmission latch circuit, the fourth PMOS transistor P4 is turned on to pull the first conduction node ① to a high level, and passes through the fourth inverter N4, the second PMOS transistor P2, and the third inverter N3. , Make Q output high level; In the follower latch circuit of the first stage, the first NMOS tube M1 is turned on and the second conduction node ② is pulled to the low level, passing through the second NOT gate N2 and the first PMOS The tube P1 and the first NOT gate N1 make DB low; in the feedforward path, the fifth PMOS tube P5 is turned on, and through the fifth transmission gate T5, the Q is high, which realizes the output Asynchronous set function, and there is no competition and risk between the two-stage circuit.
[0046] If the D flip-flop needs to be reset at a certain moment (make Q immediately low), the reverse reset signal RSTB is made low. The principle is the same as that of setting.
[0047] It is worth noting that in actual use of this embodiment, in order to reduce the transmission delay of the input signal D as much as possible, the first transmission gate T1, the second transmission gate T2, the sixth transmission gate T6, and the seventh transmission gate on the main signal path The transmission gate T7, the first inverter N1 and the third inverter N3 are slightly larger in size, and the fifth transmission gate T5 and the fifth inverter N5 in the feedforward acceleration circuit are also slightly larger in size. The third transmission gate T3, the fourth feeder T4, the second NOT gate N2, and the fourth inverter N4 on the first feeder and the second feeder may use the smallest size. The first NMOS tube M1, the second NMOS tube M2, the third NMOS tube M3, and the first PMOS tube P1, the second PMOS tube P2 and the third PMOS tube P3 used for setting and resetting can also use the smallest size for logic The seventh inverter gate N7, the eighth inverter gate N8, and the NAND gate N6 and the inverter gate N9 for generating the enable signal can all use the smallest size.
[0048] Compared with the traditional D flip-flop circuit, the fast output D flip-flop structure with asynchronous set and reset of the present invention has lower signal transmission delay, especially for complex asynchronous control and fast latch signal The design scenario can reduce unnecessary logic delay and reduce the difficulty of high-speed design.
[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be implemented Modifications or equivalent replacements without departing from the purpose and scope of the technical solution of the present invention should be covered by the scope of the claims of the present invention.
