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D trigger structure with asynchronous setting reset and rapid output

A set-reset and flip-flop technology, applied in the direction of pulse generation, electrical components, and electric pulse generation, can solve problems affecting the loop speed of the analog-to-digital converter and limit the performance of the analog-to-digital converter, so as to reduce the difficulty of high-speed design , Reduce logic delay, low transmission delay effect

Pending Publication Date: 2020-09-08
南开大学深圳研究院 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Existing D flip-flops with asynchronous set and reset functions use NAND gates to realize asynchronous set and reset, but for transmission signals, the delay of the signal passing through the NAND gate is greater than the delay passing through the inverter
Especially in the design of high-speed analog-to-digital converters, the delay time of the D flip-flop from obtaining the digital information of the previous stage to controlling the digital circuit of the next stage affects the loop speed of the analog-to-digital converter and limits the analog-to-digital converter. performance

Method used

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  • D trigger structure with asynchronous setting reset and rapid output
  • D trigger structure with asynchronous setting reset and rapid output
  • D trigger structure with asynchronous setting reset and rapid output

Examples

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Embodiment Construction

[0026] Such as Figure 2-Figure 4 Shown: a D flip-flop structure with an asynchronous set-reset fast output in this embodiment, including a follower latch circuit, a transmission latch circuit and a feed-forward acceleration circuit;

[0027] The follower latch circuit includes a first transmission gate T1, a sixth transmission gate T6, and a first NOT gate N1 coupled in sequence, and a first feeder is connected in series at both ends of the first NOT gate N1, and the fourth feeder is sequentially coupled to the first feeder. The transmission gate T4, the second conduction node, the second inverting gate N2 and the first PMOS transistor P1, the second conduction node is coupled and connected to the drain of the third PMOS transistor P3 and the drain of the first NMOS transistor M1, and the first The source and drain of the PMOS transistor P1 are connected to the first feeder;

[0028] The transmission latch circuit includes a seventh transmission gate T7, a second transmissio...

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PUM

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Abstract

The invention relates to a D trigger structure with asynchronous setting reset and rapid output. The D trigger structure comprises a following latch circuit, a transmission latch circuit and a feedforward acceleration circuit, wherein the following latch circuit is composed of a plurality of transmission gates, NOT gates, NMOS tubes and PMOS tubes; compared with a traditional D flip-flop circuit,the D trigger structure is lower in signal transmission delay, and can reduce unnecessary logic delay and reduce high-speed design difficulty especially for a design scene needing complex asynchronouscontrol and rapid signal latching.

Description

technical field [0001] The invention relates to the technical field of digital circuits, in particular to a fast-output D flip-flop structure with asynchronous reset. Background technique [0002] D flip-flop is a digital information storage device with memory function. As the basic unit of sequential circuits, it is widely used in high-speed analog-to-digital converters, computers and various large-scale digital integrated circuits. [0003] The most popular D flip-flop circuit diagram with asynchronous set and reset functions is as follows: figure 1 As shown, it consists of transmission gates T1, T2, T3, T4, and NAND gates N1, N2, N3, N4. Among them, T1, T2, N1, and N2 constitute the first-stage follower circuit, and T3, T4, N3, and N4 constitute the second-stage transmission latch circuit. [0004] In the normal working mode that does not need to set and reset, the SETB and RSTB signals are high level, and the states of the four NAND gates are only determined by the inp...

Claims

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Application Information

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IPC IPC(8): H03K3/012H03K3/037
CPCH03K3/012H03K3/0372Y02D10/00
Inventor 胡伟波燕翔国千崧冯景彬肖知明
Owner 南开大学深圳研究院
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