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Chip packaging method

A chip packaging and chip technology, applied in the manufacturing of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc., can solve problems affecting alignment accuracy, warping, etc., to reduce warping problems and inaccurate alignment. effect of risk

Active Publication Date: 2020-09-15
VIA ALLIANCE SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the unbalanced structure of the above-mentioned wafer-level package, warpage issues may occur during mold curing and other subsequent manufacturing processes, thus affecting alignment accuracy

Method used

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  • Chip packaging method
  • Chip packaging method
  • Chip packaging method

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Experimental program
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Embodiment Construction

[0043] Please refer to Figure 1A According to the chip packaging method of an embodiment of the present invention, firstly, a support structure 110 is provided. The support structure 110 is integrally formed of the same material, and the support structure 110 has a first support surface 110a, a second support surface 110b opposite to the first support surface 110a, and a connection between the first support surface 110a and the second support surface. A plurality of openings 110c on the surface 110b. In this embodiment, the material of the supporting structure 110 is, for example, metal. In addition, the supporting structure 110 may be a mesh metal structure having a plurality of openings 110c arranged in an array, such as figure 2 As shown, each opening 110c can accommodate corresponding one or more chips.

[0044] Next, carry out the step of forming a plurality of supporting conductive holes 114 (the completed figure will be described later Figure 1E shown). The supp...

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PUM

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Abstract

The invention discloses a chip packaging method, which comprises the following steps of: providing a support structure which is provided with a plurality of openings; forming a plurality of supportingconductive hole channels penetrating through the supporting structure. Temporarily fixing the support structure and a plurality of chips to a support plate, wherein the chips are respectively positioned in the openings of the support structure; forming a packaging material on the support plate, and forming a plurality of material conductive vias and a material patterned conductive layer, whereinthe material conductive vias are located in the packaging material and are respectively connected with the support conductive vias; forming a first redistribution circuit structure on the packaging material and the material patterned conductive layer, wherein the first redistribution circuit structure is electrically connected with the chip and the support conductive vias through the material patterned conductive layer and the material conductive vias; removing the carrier plate, and forming a second redistribution circuit structure.

Description

technical field [0001] The invention relates to a chip packaging technology, and in particular to a chip packaging method. Background technique [0002] The developed fan-out (Fan-out) wafer-level package (Wafer Level Package, WLP) has a smaller package size and improved electrical performance, thus providing more contacts without increasing the size of the chip package . In a general wafer-level packaging manufacturing process, the bare chip (die die) is covered with packaging materials by die molding, and the active (active) surface (active surface) of the bare chip is exposed for A dielectric layer and a patterned conductive layer are formed on the bare chip and the packaging material to produce a redistribution circuit, which is used to provide multiple contacts for connecting devices at the next level. However, due to the above-mentioned unbalanced structure of the WLP, warpage issues may occur during mold curing and other subsequent manufacturing processes, thereby a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50H01L21/56H01L21/60H01L23/535
CPCH01L21/50H01L21/561H01L21/568H01L24/02H01L24/11H01L24/97H01L23/535H01L2224/0231H01L2224/02331H01L2224/02379H01L23/3107H01L2224/18H01L2924/3511H01L2224/2518H01L2224/04105H01L2224/12105H01L2224/06181
Inventor 张文远陈伟政宫振越
Owner VIA ALLIANCE SEMICON CO LTD
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