Chip packaging method

Abstract

The invention discloses a chip packaging method, which comprises the following steps of: providing a support structure which is provided with a plurality of openings; forming a plurality of supportingconductive hole channels penetrating through the supporting structure. Temporarily fixing the support structure and a plurality of chips to a support plate, wherein the chips are respectively positioned in the openings of the support structure; forming a packaging material on the support plate, and forming a plurality of material conductive vias and a material patterned conductive layer, whereinthe material conductive vias are located in the packaging material and are respectively connected with the support conductive vias; forming a first redistribution circuit structure on the packaging material and the material patterned conductive layer, wherein the first redistribution circuit structure is electrically connected with the chip and the support conductive vias through the material patterned conductive layer and the material conductive vias; removing the carrier plate, and forming a second redistribution circuit structure.

Description

technical field [0001] The invention relates to a chip packaging technology, and in particular to a chip packaging method. Background technique [0002] The developed fan-out (Fan-out) wafer-level package (Wafer Level Package, WLP) has a smaller package size and improved electrical performance, thus providing more contacts without increasing the size of the chip package . In a general wafer-level packaging manufacturing process, the bare chip (die die) is covered with packaging materials by die molding, and the active (active) surface (active surface) of the bare chip is exposed for A dielectric layer and a patterned conductive layer are formed on the bare chip and the packaging material to produce a redistribution circuit, which is used to provide multiple contacts for connecting devices at the next level. However, due to the above-mentioned unbalanced structure of the WLP, warpage issues may occur during mold curing and other subsequent manufacturing processes, thereby a...

AI Technical Summary

Problems solved by technology

However, due to the unbalanced structure of the above-mentioned wafer-level package, warpage issues may occur during mold curing and other subsequent manufacturing processes, thus affecting alignment accuracy

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