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Chip testing method and device

A chip test and chip technology, applied in the field of information processing, can solve the problems of CP test efficiency to be improved, and achieve the effect of improving efficiency, increasing test frequency, and increasing output speed

Active Publication Date: 2020-09-22
DATANG MICROELECTRONICS TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In practical applications, the efficiency of CP testing needs to be improved

Method used

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  • Chip testing method and device

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Embodiment Construction

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the embodiments of the present application and the features in the embodiments can be combined arbitrarily with each other.

[0022] During the process of implementing this application, the inventor conducted a technical analysis on the related technology, and found that the related technology had at least the following problems, including:

[0023] The CP machine test mainly works at about 10MHz. It is not that the CP machine cannot provide a higher frequency clock. The main reason depends on the communication speed of the integrated circuit chip IO, because the IO communication speed of the integrated circuit chip is slow in the return phase....

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Abstract

The embodiment of the invention discloses a chip testing method and device. The method comprises: after it is detected that a wafer CP test is conducted on a chip, obtaining output time delay information of an input and output IO port, used for outputting a return result of a test vector, of the chip; controlling the numerical value of the output time delay to be reduced; and outputting a return result of the test vector according to the reduced output time delay.

Description

technical field [0001] The embodiments of the present application relate to the field of information processing, in particular to a chip testing method and device. Background technique [0002] Integrated circuit chips generally include a CPU state and a test state. Before becoming a product, they must pass a wafer-level CP (Chip Probing, wafer test) test in the test state. In order to improve test efficiency, the test vector pattern is usually carried out according to the clock clk change. The clock and data of the pattern are input into the chip through the input / output (IO) port for use, and the result is returned to the CP machine after the internal operation of the chip is completed. [0003] In practical applications, the efficiency of CP testing needs to be improved. Contents of the invention [0004] In order to solve any of the above technical problems, embodiments of the present application provide a chip testing method and device. [0005] In order to achieve...

Claims

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Application Information

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IPC IPC(8): G01R31/28
CPCG01R31/2882
Inventor 刘蕊丽李紫金
Owner DATANG MICROELECTRONICS TECH CO LTD
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