Semiconductor packaging structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor packaging structure and a semiconductor packaging structure manufacturing method, and relates to the technical field of semiconductors. The semiconductor packaging structure comprises a substrate, a first chip, a second chip, a first vertical bonding wire and a filling adhesive, wherein the second chip is a flip chip, and comprises a first convex point, the first chip is arranged on the substrate, the second chip is arranged on one side, far away from the substrate, of the first chip in an offset stacking manner, the first convex point is arranged at a position, which is close to one side of the first chip and is not contacted with the first chip, of the second chip, one end of the first vertical bonding wire is connected with the first convex point, the other end of the first vertical bonding wire is connected with the substrate, and the filling adhesive is arranged between the second chip and the substrate, and is used for fixing the first vertical bonding wire and supporting the second chip. According to the invention, a semiconductor packaging structure with a stable structure can be obtained by arranging a vertical bonding wire and a filling adhesive.

Description

technical field [0001] The present application relates to the technical field of semiconductors, and in particular, to a semiconductor packaging structure and a manufacturing method of the semiconductor packaging structure. Background technique [0002] With the development of semiconductor technology, while electronic products tend to be miniaturized, their performance and memory requirements are also getting higher and higher. In the existing technology, the semiconductor packaging structure adopts multiple chip stacking (Stack-Die) technology or FOW (flow over wire) stacking technology to meet the growing demand. However, in the semiconductor package manufactured based on the prior art, as the number of chip stacking layers increases, the wiring length is longer, and it is difficult to perform precise wiring, which may easily lead to unstable wiring. Not only that, as the height of the chip stack increases, the greater its inclination, the more unstable the underlying st...

AI Technical Summary

Problems solved by technology

However, the semiconductor package based on the existing technology, as the number of layers of the chip stack increases, the length of the wire bonding is longer, and it is difficult to accurately wire the wires, which may easily lead to unstable wire bonding

Not only that, as the height of the chip stack increases, the greater its inclination, the more unstable the underlying structure of the chip, which may cause the collapse / collapse of the stacked chip structure, resulting in product damage, which makes the existing multi-layer chip stacked semiconductor Package structure is not stable

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