Pi-type gate polycrystal compatible with dual-gate oxide high-low voltage CMOS process and capable of improving stability of device and manufacturing method thereof
A production method, high and low voltage technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the unevenness of gate polycrystalline surface, affect the long-term reliability of PMOS gate polycrystalline surface morphology products, and affect PMOS devices Electrical performance and other issues to achieve the effect of improving flatness, improving product yield and market competitiveness, and improving concentration matching
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Embodiment 1
[0063] see Figure 1 to Figure 7 A π-type gate polycrystalline manufacturing method compatible with a double-gate oxide high-voltage and low-voltage CMOS process to improve device stability, comprising the following steps:
[0064] 1) An N-type well implantation region is formed on the substrate 24, and an N-type well 13 is formed in the N-type well implantation region. A self-aligned P-type well region is formed outside the N-type well implantation region, and a self-aligned P-type well 20 is formed inside.
[0065] 2) Form a P-type MOS lightly doped source-drain implantation region 12 and a P-type MOS source-drain implantation region 17 in the N-type well implantation region, and complete the implantation of the P-type MOS lightly doped source-drain and P-type MOS source-drain respectively .
[0066] 3) Form a LOCOS field oxide layer 11 of n angstroms on the surface of the N-type well implanted region and the self-aligned P-type well region, and the LOCOS field oxide layer...
Embodiment 2
[0085] The pre-order process is the same as implementation 1:
[0086] 1) On the gate oxide layer, a fAm MOS gate polycrystalline layer is deposited by a low-pressure chemical vapor deposition method; the gate polycrystalline layer is doped by an in-situ doping process.
[0087] The in-situ doping process has high requirements for equipment and process control, but it can simplify the gate polycrystalline deposition doping process.
[0088] 2) Depositing a silicon nitride dielectric layer with a thickness of g angstroms on the gate polycrystalline layer by using a low-pressure chemical vapor deposition process, and using a photolithographic etching process to complete gate polycrystalline etching in a selected area;
[0089] The steps for determining the silicon nitride dielectric layer are as follows:
[0090] 2.1) The thickness of the silicon nitride film is selected according to the energy of the subsequent source-drain implantation, so as to meet the process requirements ...
Embodiment 3
[0093] The pre-order process is the same as implementation 1, see figure 2 :
[0094] 1) Depositing a first layer of polycrystalline film and an oxynitride dielectric protection layer sequentially on the field oxide layer. Realize the integration of polycrystalline resistors and high and low voltage compatible CMOS main processes.
[0095] 2) After the deposition of the first polycrystalline film, the resistivity of the polycrystalline film layer is first adjusted by N-type impurity general injection process, and then P-type impurities are injected into the polycrystalline resistance area requiring a low temperature coefficient to achieve long-term stability Made of high-precision linear polycrystalline resistors.
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