π-type gate polycrystal compatible with double gate oxide high and low voltage cmos process to improve device stability and manufacturing method thereof
A production method, high and low voltage technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the unevenness of the gate polycrystalline surface, affect the electrical performance of PMOS devices, and affect the long-term products of PMOS gate polycrystalline surface morphology Reliability and other issues, to achieve the effect of improving the voltage coefficient and near-zero bias capacitor voltage symmetry, improving the smoothness of the gate polycrystalline surface of PMOS devices, and improving the concentration matching
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Embodiment 1
[0063] see Figure 1 to Figure 7 , a π-type gate polycrystalline fabrication method compatible with double gate oxide high and low voltage CMOS process to improve device stability, comprising the following steps:
[0064] 1) An N-type well implanted region is formed on the substrate 24, and an N-type well 13 is formed in the N-type well implanted region. A self-aligned P-type well region is formed outside the N-type well implanted region, and a self-aligned P-type well 20 is formed inside.
[0065] 2) P-type MOS lightly doped source-drain implantation region 12 and P-type MOS source-drain implantation region 17 are formed in the N-type well implantation region, and the implantation of P-type MOS lightly doped source-drain and P-type MOS source-drain implantation is completed respectively .
[0066] 3) A LOCOS field oxide layer 11 of n angstrom is formed on the surface of the N-type well implantation region and the self-aligned P-type well region, and the LOCOS field oxide la...
Embodiment 2
[0085] The pre-procedure process is the same as implementation 1:
[0086] 1) A low-pressure chemical vapor deposition method is used to deposit a f-Angstrom MOS gate polycrystalline layer on the gate oxide layer; the gate polycrystalline layer is doped by an in-situ doping process.
[0087] The in-situ doping process has higher requirements on equipment and process control, but can simplify the gate polycrystalline deposition doping process.
[0088] 2) depositing a silicon nitride dielectric layer with a thickness of g Angstrom on the gate polycrystalline layer by using a low pressure chemical vapor deposition process, and using a photolithography etching process to complete the gate polycrystalline etching in the selected area;
[0089] The steps to determine the silicon nitride dielectric layer are as follows:
[0090] 2.1) The thickness of the silicon nitride film is selected according to the energy of the subsequent source-drain implantation, so as to meet the process r...
Embodiment 3
[0093] The pre-procedure process is the same as implementation 1, see figure 2 :
[0094] 1) A first layer of polycrystalline film and an oxynitride dielectric protective layer are sequentially deposited on the field oxide layer. Realize the integration of polycrystalline resistors and high and low voltage compatible CMOS main processes.
[0095] 2) After the first layer of polycrystalline film is deposited, firstly adopt the N-type impurity injection process to adjust the resistivity of the polycrystalline film layer, and then inject P-type impurities into the polycrystalline resistance region requiring low temperature coefficient to achieve long-term stability of high-precision linear polycrystalline resistors.
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