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Formation method of pattern layout

A pattern and layout technology, applied in the field of pattern layout formation, can solve problems such as damage and unstable operation of storage units, and achieve the effect of saving process steps

Active Publication Date: 2022-03-04
FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to increase the memory capacity, the size of the storage unit of the memory needs to be reduced, but a large reduction in the size of the storage unit will cause other problems, making the operation of the storage unit unstable or damaged

Method used

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  • Formation method of pattern layout
  • Formation method of pattern layout
  • Formation method of pattern layout

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Embodiment Construction

[0038] The following detailed description refers to the content shown in the relevant drawings to illustrate the embodiments that can be implemented according to the present invention. These examples provide sufficient detail to enable those skilled in the art to fully understand and practice the present invention. Structural or electrical modifications can still be made and applied to other embodiments without departing from the scope of the present invention.

[0039] Therefore, the following detailed description is not intended to limit the present invention. The scope of the invention is defined by its claims. Those with equivalent meanings to the claims of the present invention shall also fall within the scope of the present invention.

[0040] The present invention relates to a structure of a semiconductor integrated circuit, for example, an active area structure of a dynamic random access memory (DRAM).

[0041] like Figures 1A-6B as shown, 1A to 6B A method for f...

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Abstract

The invention discloses a method for forming a pattern layout. At least the plurality of first patterns formed on the substrate itself has a plurality of first wide portions and first narrow portions arranged alternately, wherein the plurality of first narrow portions are automatically formed after the etching step due to their small size. is removed, leaving a plurality of arrayed first wide portions. The left multiple first wide portions can be used as a mask layer for subsequent active regions, and then subsequent steps form a plurality of active regions arranged in a checkerboard pattern in the substrate. With the method of the present invention, the goal of saving process steps can be achieved.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular to a method for forming a pattern layout of an active area. The forming method of the present invention helps to simplify the process. Background technique [0002] In recent years, the design of electronic products generally has multi-functional and fast processing capabilities. In order to increase processing capabilities, such as computer systems or multi-functional electronic products, large-capacity dynamic random access memory (DRAM) is required. In order to increase the memory capacity, the size of the storage unit of the memory needs to be reduced, but a large reduction in the size of the storage unit will cause other problems, making the operation of the storage unit unstable or damaged. [0003] Semiconductor components are generally based on the active layer unit defined on the substrate to form the desired component structure. Therefore, the active layer unit on t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/033H01L27/108H10B12/00
CPCH10B12/00H10B12/50
Inventor 许耀光朱贤士周运帆王超雄
Owner FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD