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Circuitry and method

A circuit and transaction technology, applied in the field of circuits, can solve problems such as not being able to be activated at the same time

Pending Publication Date: 2020-12-08
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Pause and ATS are functions that are enabled separately and cannot be enabled at the same time

Method used

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  • Circuitry and method
  • Circuitry and method
  • Circuitry and method

Examples

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Embodiment Construction

[0036] Referring now to the accompanying drawings, figure 1 A circuit operating according to a so-called Peripheral Component Interconnect Express (PCIe) arrangement is schematically shown. In the depicted embodiment of PCIe, so-called endpoints 100 interact with peripheral devices such as memory 110 , eg read data from or write data to memory 110 . Endpoints operate according to virtual addresses (VA), while the ultimate interaction with memory 110 occurs according to physical addresses (PA). Therefore, in order to execute a data processing transaction initiated by the endpoint 100, it is necessary to convert VA to PA.

[0037] The PCIe functionality discussed here (in contrast to the previously proposed figure 1 PCIe circuitry or use some of the PCIe features Figure 5 related to the example implementation of ) related to the PCIe standard from generation 4.0 onwards (that is to say higher), as defined in the standard published at https: / / pcisig.com / specifications, the co...

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Abstract

The invention provides circuitry and a method. The circuitry comprises a transaction interface to receive a data handling transaction from an upstream device; translation circuitry to access a set ofaddress mappings between virtual memory addresses and physical memory addresses in a physical memory address space; and control circuitry to receive a memory region request from the upstream device, requesting that a memory region in the virtual memory address space including the target virtual memory address be made available, to initiate handling of the memory region request and to provide a response to the upstream device in dependence upon the handling of the memory region request.

Description

technical field [0001] The present disclosure relates to a circuit and method. Background technique [0002] In some circuit embodiments that use memory address translation, a device's translation can be configured such that in the event of a translation failure, the failed transaction will be suspended so that software (such as the operating system) can decide what to do with it. This parsing process can be started automatically by the memory management unit and is invisible to suspended devices. Then, the memory management unit can wait until the transaction is retried or terminated. [0003] However, pause failures can lead to deadlocks in some cases. As a result, general-purpose operating systems (such as Linux) generally cannot enable halt failures in any device (if it causes a deadlock). [0004] Another system dealing with these issues is the ATS (Address Translation Service) and PRI (Page Request Interface) functions using the PCIe (Peripheral Component Interconne...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/1027
CPCG06F12/1027G06F2212/657G06F13/4221G06F2212/684G06F12/1036G06F2212/1041G06F12/1009
Inventor 安德鲁·布鲁克菲尔德·斯维尼
Owner ARM LTD
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