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Semiconductor test structure and quality test method of semiconductor passivation layer

A test structure and semiconductor technology, which is applied in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve the problems of high cost and long verification cycle, and achieve the effect of reducing costs and shortening the test cycle

Active Publication Date: 2020-12-18
晶芯成(北京)科技有限公司
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Problems solved by technology

[0003] However, the existing evaluation of the quality of the passivation layer is verified by the customer's cooperation with the temperature cycle experiment of the product level (that is, the finished product made through packaging and other processes), which has problems such as long verification period and high cost.

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  • Semiconductor test structure and quality test method of semiconductor passivation layer
  • Semiconductor test structure and quality test method of semiconductor passivation layer
  • Semiconductor test structure and quality test method of semiconductor passivation layer

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Embodiment Construction

[0036] In order to make the purpose, advantages and features of the present invention clearer, the semiconductor test structure and the quality test method of the semiconductor passivation layer proposed in the present invention will be further described in detail below. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0037] An embodiment of the present invention provides a semiconductor test structure, the semiconductor test structure includes a first metal layer, an insulating layer, a second metal layer, a passivation layer and a plurality of pads, the first metal layer includes at least one A serpentine structure, the insulating layer covers the first metal layer and fills the gaps of the serpentine structure, the second metal layer is formed on the insulating layer, and the second metal layer includes tw...

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Abstract

The invention provides a semiconductor test structure and a quality test method of a semiconductor passivation layer. The semiconductor test structure comprises a first metal layer which comprises atleast one snake-shaped structure; an insulating layer which covers the first metal layer and fills the gap of the serpentine structure; a second metal layer which is formed on the insulating layer, wherein the second metal layer comprises two comb-shaped structures which are oppositely arranged in a staggered mode, and comb teeth of the two comb-shaped structures are interspersed with each other;a passivation layer which covers the second metal layer and the insulating layer exposed out of the comb tooth gaps of the comb-shaped structure; and a plurality of bonding pads which are respectivelyconnected with the two ends of the first metal layer and the second metal layer. According to the technical scheme, whether defects exist in the passivation layer or not can be determined in time, the test period is shortened, and therefore, the cost is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a semiconductor test structure and a quality test method for a semiconductor passivation layer. Background technique [0002] In the manufacturing process of the semiconductor device, a passivation layer (Passivation) is covered on the uppermost layer of the semiconductor device to protect the underlying structure from damage. However, factors such as the potential high stress of the passivation layer, interface delamination, and dielectric defects will make it sensitive to temperature changes, which will lead to cracks in the passivation layer during chip use, resulting in chip failure (metal interconnection disconnected wire, unsealed chip surface, etc.). Therefore, the industry reliability standard stipulates that a temperature cycle (TC, Temperature cycle) test is required for quality evaluation for the change of the passivation layer process. ...

Claims

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Application Information

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IPC IPC(8): H01L21/66
CPCH01L22/32
Inventor 周山王丽雅俞佩佩
Owner 晶芯成(北京)科技有限公司
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