Superconducting pipeline circuit and processor

Abstract

The invention provides a superconducting pipeline circuit, which at least comprises a first reset register group, a first logic combinational circuit, a second reset register group and a second logiccombinational circuit, and the first reset register group and the second reset register group are used for receiving data input under the control of enable signals and outputting the received input data under the control of a first clock. the first logic combinational circuit receives output data of the first register set capable of being reset and outputs the data to the second reset register group after the data is operated under the control of a first clock. The second logic combinational circuit receives the output data of the second register set capable of being reset and outputs the dataafter operating the data under the control of the first clock; the second logic combination circuit is also used for generating an internal reset signal and a blocking signal; the blocking signal isused to control validity and invalidation of the enable signal, and the internal reset signal is used to control reset of the first and second reset register groups.

Description

technical field [0001] The invention relates to the field of superconducting electronic circuits, in particular to a superconducting pipeline circuit and a processor. Background technique [0002] Rapid Single Flux Quantum (RSFQ) superconducting circuits are made of superconducting materials using the physical principles of Josephson junctions. The circuit works by using the presence or absence of conduction current in the Josephson junction to flag 0 and 1. Superconducting circuits have the characteristics of low power consumption and fast operation speed, and are the key development direction of electronic circuits in the future. [0003] The mainstream design of the current RSFQ superconducting processor is to use traveling wave pipelines. Any path on the data path that passes through a logic gate requires all other data paths to pass through a logic gate to achieve clock alignment. If there is no corresponding logic gate element, then It is necessary to add a D flip-fl...

AI Technical Summary

Problems solved by technology

However, unlike the traditional pipeline concept, since the transmission of superconducting signals needs to be transmitted through the Josephson transmission line (JTL), its propagation speed is much lower than the transmission speed of electrical signals, so a JTL spanning several pipeline stages will cause a huge time delay. , although superconducting circuits can operate at high speeds, it is difficult to achieve data feedback

That is to say, the data is "one-time" input and "one-time" output. If there is a need to forward the data in the middle, it will face great design difficulties.

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