Semiconductor device preparation method and semiconductor device

Abstract

The invention discloses a semiconductor device preparation method and a semiconductor device, and the method comprises the steps of forming a conductive stacking layer on a substrate, depositing a first insulating dielectric layer covering the conductive stacking layer at a first temperature, and patterning the first insulating dielectric layer and the conductive stacking layer of a peripheral circuit region of the substrate, so as to form a gate structure; performing heat treatment on the first insulating dielectric layer, the conductive stacking layer, the gate structure and the substrate; depositing a second insulating dielectric layer at a second temperature higher than the first temperature, enabling the second insulating dielectric layer to at least cover the first insulating dielectric layer located in the unit array region, patterning the first insulating dielectric layer and the second insulating dielectric layer in the unit array region; taking the patterned first insulatingdielectric layer and the patterned second insulating dielectric layer as masks, and etching the conductive stack layer to form a bit line structure in the unit array region. The method is favorable for forming a bit line structure with a vertical profile to improve the performance of the semiconductor device.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for preparing a semiconductor device and a semiconductor device. Background technique [0002] With the development of technology, the concentration of semiconductor devices has been increased, and the critical dimensions of semiconductor devices have been reduced. When preparing semiconductor devices such as storage devices, the small critical dimensions will make it impossible to simultaneously form the bit line structure in the cell array area and the gate structure in the peripheral circuit area of ​​the storage device. Usually, the peripheral circuit area is patterned first to Form the gate structure. At this time, a layer of insulating dielectric layer will be used as a barrier layer to protect the structural layer of the cell array area that does not need to be patterned in this step. After the gate structure of the peripheral circuit area is completed, it will be de...

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Problems solved by technology

[0003] Since the entire semiconductor structure is subjected to rapid thermal annealing after the formation of the gate structure and before the deposition of the second insulating dielectric layer, the processing conditions of the insulating dielectric layers in the multilayer structure in which the cell array region is used as a mask are different, As a result, the etch rates of the above-mentioned multi-layer insulating dielectric layers are different during subsequent etching, and it is easy to form a mask structure with a tapered profile, which in turn affects the profile of the bit line

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