A kind of semiconductor device preparation method and semiconductor device

Abstract

The invention discloses a method for preparing a semiconductor device and a semiconductor device. By forming a conductive stack layer on a substrate, depositing a first insulating dielectric layer covering the conductive stack layer at a first temperature, first patterning the peripheral circuit area of ​​the substrate The first insulating dielectric layer and the conductive stacked layer are used to form the gate structure, and heat treatment is performed on the first insulating dielectric layer, the conductive stacked layer, the gate structure and the substrate; and the second temperature is deposited at a second temperature higher than the first temperature Insulating dielectric layer, the second insulating dielectric layer at least covers the first insulating dielectric layer located in the cell array area, patterning the first insulating dielectric layer and the second insulating dielectric layer in the cell array area, so that the patterned first insulating dielectric layer Layer and the second insulating dielectric layer are used as a mask to etch the conductive stacked layer to form a bit line structure in the cell array area. The method is beneficial to forming a bit line structure with a vertical profile and improving the performance of semiconductor devices.

Description

Technical field [0001] The present invention relates to the field of semiconductor, and more particularly to a semiconductor device preparation method and a semiconductor device. Background technique [0002] With the development of technology, the concentration degree of semiconductor devices is improved, and the key size of the semiconductor device is reduced. When the semiconductor device such as memory is prepared, the smaller key size causes the bit line structure located in the unit array region in the memory device and the gate structure located in the peripheral circuit area, which is usually patterned to the peripheral circuit region. The gate structure is formed. At this time, a layer of insulating dielectric layer is used as a barrier layer to protect this step without the graphical cell array region structure layer, after completing the gate structure of the peripheral circuit area, then deposition on the insulating dielectric layer. At least one layer of insulating d...

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Problems solved by technology

[0003] Since the entire semiconductor structure is subjected to rapid thermal annealing after the formation of the gate structure and before the deposition of the second insulating dielectric layer, the processing conditions of the insulating dielectric layers in the multilayer structure in which the cell array region is used as a mask are different, As a result, the etch rates of the above-mentioned multi-layer insulating dielectric layers are different during subsequent etching, and it is easy to form a mask structure with a tapered profile, which in turn affects the profile of the bit line

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