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Adaptive SGPIO decoder achieved through logic chip and program

A logic chip and self-adaptive technology, applied in the field of signal decoding, can solve the problem of consuming logic resources and achieve the effect of simplifying PCB lines and reducing occupation

Active Publication Date: 2021-01-29
SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the traditional complex programmable logic device needs to implement two sets of different SGPIO decoding circuits, consuming more logic resources

Method used

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  • Adaptive SGPIO decoder achieved through logic chip and program
  • Adaptive SGPIO decoder achieved through logic chip and program
  • Adaptive SGPIO decoder achieved through logic chip and program

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Embodiment Construction

[0035] It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0036] The present invention is described below in conjunction with accompanying drawing, wherein, figure 1 It is a schematic diagram of the SGPIO signal transmitted by the South Bridge chip; figure 2 It is a schematic diagram of the SGPIO signal transmitted by the RAID card; image 3 It is a schematic diagram of the SGPIO decoding circuit; Figure 4 It is a schematic diagram of an adaptive SGPIO decoder implemented by a logic chip in an embodiment of the present invention; Figure 5 is a schematic diagram of the architecture of the logic chip in the embodiment of the present invention; Image 6 It is a schematic diagram of the position of the detection mark detected by the detection and counting module in the SGPIO signal in the embodiment of the present invention; Figure 7 It is a flowchart of counting and ana...

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Abstract

The invention discloses an adaptive SGPIO decoder achieved through a logic chip and a program. The logic chip is electrically connected with the output end of a channel selector . The input end of thechannel selector is respectively connected with the RAID card and the south bridge chip; the RAID card is electrically connected with the SAS hard disk, and the south bridge chip is electrically connected with the SATA hard disk; and the logic chip is electrically connected with the SAS hard disk indicating lamp and the SATA hard disk indicating lamp. According to the invention, the channel selector is connected with the logic chip, and only one group of SGPIO channels is required to be connected to the logic chip, so that a PCB circuit can be simplified, and the occupation of IO ports of thelogic chip is reduced; for the logic chip, the decoding of two different SGPIO signals can be achieved by only adopting one group of SGPIO decoding circuits, so that the logic resource consumption ofthe logic chip is reduced, and the cost is reduced. SGPIO signal analysis of different lengths of other special applications can be coped with only a very small modification program, and it is convenient for manufacturers to design control of hard disk indicator lamps according to product requirements of the manufacturers.

Description

technical field [0001] The invention relates to the field of signal decoding, in particular to an adaptive SGPIO decoder and a program realized by a logic chip. Background technique [0002] The SGPIO bus is a bus used by SATA / SAS hard disks in general-purpose servers and disk array servers. The main purpose of SGPIO is to transmit status signals (Active / Locate / Error) of up to 8 hard disks with fewer signal lines and pass through The control unit controls the server hard disk indicator light according to the status signal, so that the user or system administrator can know the working status of each storage device on the system in real time. [0003] SGPIO is composed of four signals: SClock, SLoad, SDataOut, and SDataIn. Data is output from the main control (PCH or RAID card) on the rising edge of SClock, and the receiving end (complex programmable logic device) needs to capture valid data on the falling edge of SClock. . In practical applications, the same system may use ...

Claims

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Application Information

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IPC IPC(8): G06F13/42G06F11/32
CPCG06F13/4282G06F11/325
Inventor 陆俊宇
Owner SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
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