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Pattern making method and pattern layout

A production method and pattern technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve the problems of low yield rate of fine pattern manufacturing process and complicated fine pattern production process

Active Publication Date: 2022-04-19
FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The main purpose of this application is to provide a pattern making method and pattern layout to solve the problem that the fine pattern making process in the prior art is relatively complicated, resulting in a low process yield of fine patterns

Method used

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  • Pattern making method and pattern layout
  • Pattern making method and pattern layout
  • Pattern making method and pattern layout

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Embodiment Construction

[0030] It should be pointed out that the following detailed description is exemplary and intended to provide further explanation to the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0031] It should be noted that the terminology used here is only for describing specific implementations, and is not intended to limit the exemplary implementations according to the present application. As used herein, unless the context clearly dictates otherwise, the singular is intended to include the plural, and it should also be understood that when the terms "comprising" and / or "comprising" are used in this specification, they mean There are features, steps, operations, means, components and / or combinations thereof.

[0032] It will be understood that when an element such as a layer, film, region, or substrate is referred to as ...

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PUM

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Abstract

The present application provides a pattern making method and a pattern layout, the method comprising: forming a pre-pattern on a substrate, the pre-pattern includes a plurality of pre-structures arranged at intervals along a first direction, the pre-structure includes a ring structure, a first pad structure and a second pad structure, the ring structure includes a first vertical portion, a first horizontal portion, a second vertical portion, and a second horizontal portion connected end to end in sequence, wherein the first horizontal portion contacts the first pad structure , the second horizontal part is in contact with the second pad structure; the pre-pattern is etched to remove the first part and the second part of the annular structure, so that the pre-structure forms a spacer structure, and the spacer structure includes first conductive lines and second Two wires, wherein the first wire includes a first pad structure, at least part of a first horizontal portion, and at least a portion of a first vertical portion, and the second wire includes a second pad structure, at least a portion of a second horizontal portion, and at least a portion of a first vertical portion Two vertical parts.

Description

technical field [0001] The present application relates to the field of semiconductors, and in particular, to a pattern manufacturing method and pattern layout. Background technique [0002] With the rapid growth of the semiconductor industry, it has become a trend to integrate semiconductor devices in a limited area of ​​a semiconductor substrate. Typically, attempts to increase the density of semiconductor devices have resulted in the formation of fine patterns. Various techniques have been proposed for forming fine patterns with nanoscale critical dimensions, for example, ranging in size from about several nanometers to about tens of nanometers. However, the manufacturing process of the fine pattern in the prior art is relatively complicated, resulting in a low process yield of the fine pattern. [0003] The above information disclosed in the Background section is only to enhance the understanding of the background of the technology described herein, therefore, the Backg...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498H01L21/48
CPCH01L23/49838H01L21/4846
Inventor 张钦福冯立伟童宇诚
Owner FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD