Delay line structure and delay jitter correction method thereof

Abstract

The invention discloses a delay line structure and a delay jitter correction method thereof. The delay line structure comprises N delay units and N selectors. The output end of the N-1th delay unit isconnected to the first input end of the N-1th selector and the input end of the Nth delay unit, the N-1th selector inputs the N-1th selection signal, and the N-1th selector outputs the N1th selectionsignal; the output end of the Nth time delay unit is connected to the first input end of the Nth selector, the output end of the Nth selector is connected to the second input end of the N1th selector, and the Nth selector inputs an Nth selection signal. The time delay units and the selectors are stacked forwards according to the rule until the input ends of the first time delay units are connected with input signals and the output ends of the first selectors are connected with output signals. According to the structure, delay control can be carried out on the clock at the sending end or the receiving end to meet the requirement of receiving timing, and the jitter of the delay of the delay line can be reduced.

Description

technical field [0001] The invention relates to the technical field of digital communication, in particular to a delay line structure and a correction method for delay jitter thereof. Background technique [0002] In modern communication networks, due to the increase in data rate, the transmission rate of the chip interface is getting faster and faster. Traditional digital interfaces transmit data only on the rising or falling edge of the clock. In order to increase the transmission rate, on the premise of not changing the clock frequency, data is transmitted on the rising and falling edges of the data at the same time, and the data transmission rate will be doubled. Take the timing sequence of the Ethernet transmission interface RGMII as an example, see figure 1 As shown, RXC is the associated clock, and RXD / RX_CTL is the associated data. It can be seen that the data jumps on the rising and falling edges of RXC. Assuming that the transition edge of the RXC at the sending...

AI Technical Summary

Problems solved by technology

Traditional digital interfaces transmit data only on the rising or falling edge of the clock

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