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Semiconductor structure and forming method thereof

A semiconductor and isolation structure technology, applied in the field of semiconductor structure and its formation, can solve the problems of difficult channel and poor channel control ability of the gate structure, and achieve high uniformity, high consistency, optimized The effect of electrical properties

Pending Publication Date: 2021-02-02
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the ability of the gate structure to control the channel becomes worse, and the gate voltage pinches off the channel. The difficulty of the channel is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (short-channel effects, SCE) more prone to occur

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

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Embodiment Construction

[0012] Currently formed devices still suffer from poor performance. The reasons for the poor performance of the device are analyzed in conjunction with a method of forming a semiconductor structure.

[0013] Figure 1 to Figure 5 It is a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0014] Such as figure 1 As shown, a base is provided, the base includes a substrate 1 and fins 2 located on the substrate 1; the base includes an isolation region II and a device region I, and the fins located in the device region I 2 is a device fin 21 , and the fin 2 located in the isolation region II is a dummy fin 22 ; an isolation layer 4 is formed on the fin 2 exposing the substrate 1 .

[0015] Such as figure 2 As shown, the dummy fin portion 22 on the isolation region 1 is etched to form the remaining dummy fin portion 3, the top of the remaining dummy fin portion 3 is lower than the top surface of the isolation layer 4, an...

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Abstract

The invention provides a semiconductor structure and a forming method thereof. The forming method comprises the steps of providing a base, wherein the base comprises a substrate and fin parts locatedon the substrate, the base comprises an isolation region and a device region which are adjacent, the fin parts located in the device region are device fin parts, and the fin parts located in the isolation region are pseudo fin parts; forming a pseudo gate structure stretching across the fin parts; forming source and drain doped regions in the fin parts on the two sides of the pseudo gate structure; removing the pseudo gate structure to form a gate opening; and removing the pseudo fin parts in the gate opening. According to the embodiment of the invention, in the process of forming the pseudo gate structure, the sparsity degree consistency of the fin parts in the isolation region and the device region is good, so that the pseudo gate structure in the device region and the isolation region is good in height uniformity, and the distance between the top of the gate opening and the top of the device fins is equal to the distance between the top of the gate opening and the top of the pseudofins; a gate structure is subsequently formed in the gate opening, the height consistency of the gate structure in the isolation region and the device region is good, and the electrical performance ofthe semiconductor structure is optimized.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor , MOSFET) channel length has been shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the ability of the gate structure to control the channel becomes worse, and the gate voltage pinches off the channel. The channel becomes more and more difficult, making subthreshold leakage (subthreshold leakage), the so-called short-channel effect (shor...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/7855H01L29/66477H01L29/66545
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP
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