Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; forming a plurality of initial pseudo gate structures on the substrate, wherein each initial gate structure comprises a first pseudo gate layer, a first mask layer and a second pseudo gate layer; forming a side wall material layer on the side wall and the top surface of the initial pseudo gate structure; forming a dielectric material layer on the substrate; and first planarization processing is carried out on the dielectric material layer and the side wall material layer until the top surface of the second pseudo gate layer is exposed, and the grinding rate of the first planarization processing on the second pseudo gate layer is smaller than the grinding rate of the first planarization processing on the dielectric material layer and the side wall material layer. According to the scheme, it can be guaranteed that the first planarization processing is stopped on the surface of the second pseudo gate layer, a flat processing interface is achieved, and meanwhile the uniformity of the height of the initial side wall is effectively improved. And the top surface of the formed initial dielectric layer is higher than the top surface of the first pseudo gate layer, so that the problem of short circuit of subsequent adjacent gate structures can be effectively avoided, and the performance of the formed semiconductor structure is improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background technique [0002] With the reduction of technology nodes, the traditional gate dielectric layer is continuously thinner, and the leakage of transistors increases accordingly, causing problems such as waste of power consumption of semiconductor devices. In order to solve the above problems, the prior art provides a solution of replacing the polysilicon gate with a metal gate. Among them, the gate last process is a main process for forming the metal gate. [0003] However, during the gate-last process, the metal material of the metal gate deteriorates the isolation performance of the dielectric layer in the semiconductor structure, thereby affecting the performance of the semiconductor structure. SUMMARY OF THE INVENTION [0004] The technical problem solved by the present invention is ...

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Problems solved by technology

[0003] However, during the gate-last process, the metal material of the metal gate deteriorates the isolation performance of the dielectric layer in the semiconductor structure, thus affecting the performance of the semiconductor structure

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