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Memory and read-write method thereof

A read-write method and memory technology, applied in the field of memory, can solve problems such as large leakage current of memory

Active Publication Date: 2021-02-09
CETHIK GRP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The main purpose of this application is to provide a memory and its reading and writing method to solve the problem of large memory leakage current caused by the 3D stacking technology in the prior art

Method used

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  • Memory and read-write method thereof
  • Memory and read-write method thereof
  • Memory and read-write method thereof

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Experimental program
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Embodiment

[0054] The memory is structured as figure 1 shown. The memory is composed of 512 storage layers 10 arranged in the first direction, only four storage layers 10 are shown in the figure, and each storage layer 10 is composed of a storage array, a plurality of switches 12, a plurality of word lines 13, a plurality of One bit line 14 and one source line 15 are formed. In the storage layer 10, the number of switches 12 is the same as the number of columns of the memory cells 11, the number of bit lines 14 is the same as the number of rows of the memory cells 11, and the number of word lines 13 is the same as the number of switches 12, wherein the switches 12 are transistors , the storage unit 11 includes a selector and an MTJ. The specific connection relationship is as figure 1 shown. Specifically, such as image 3 As shown, the storage bit 111 is an MTJ CoFeB / MgO system, specifically including a free layer, a barrier insulating layer and a fixed layer, the selector 112 is a d...

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PUM

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Abstract

The invention provides a memory and a read-write method thereof. The memory includes a plurality of memory layers arranged along a first direction, each memory layer including: a memory array including a plurality of memory cells arranged in an array manner and a plurality of bit lines arranged at intervals; a switch unit which includes a plurality of switches, a plurality of spaced word lines, and at least one source line. According to the arrangement mode, bit lines and source lines of the adjacent storage layers are independent from each other, voltage can be independently applied, and whenone of the storage layers is selected, no voltage difference exists between the bit lines and the source lines of the adjacent storage layers, so that the electric leakage phenomenon does not exist,and the electric leakage of the memory is relatively small. According to the memory, different memory layers do not share the bit lines and the source lines, so that random read-write operation can berealized, and the performance of the memory is improved.

Description

technical field [0001] The present application relates to the field of memory, and in particular, to a memory and a method for reading and writing the same. Background technique [0002] In the prior art, in order to increase the storage capacity of the memory, it is necessary to provide the storage density of the memory. [0003] In the prior art, there are usually three ways to increase the storage density. One is to reduce the size of the storage unit. However, this method has basically reached the limit due to the limitation of the production equipment, the level of technology and the characteristics of the storage unit; the other is to reduce the size of the storage unit. One is to increase the storage state of the storage unit. Although there are various reports in the laboratory in this scheme, each die has consistent polymorphic characteristic parameters in a large number of wafers, so as to realize polymorphic writing and It is very difficult to read; the third is ...

Claims

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Application Information

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IPC IPC(8): G11C5/02G11C7/10G11C7/12G11C8/08
CPCG11C5/02G11C7/12G11C8/08G11C7/1069G11C7/1096G11C7/10
Inventor 熊保玉何世坤陆宇
Owner CETHIK GRP