A novel 3D cross-point memory structure formed by XTACKING to improve memory array efficiency and achieve scaling

Abstract

A novel memory contact scheme for a three-dimensional cross-point memory is presented that allows greater memory density per unit area on a chip or wafer as compared to certain known contact schemes.A chip includes a first wafer supporting a first electronic component and a first plurality of vertical interconnect channels, the first electronic component including any one or any combination of abit line decoder and a word line decoder. The chip also includes a second wafer supporting a second electronic component and a second plurality of vertical interconnect channels, the second electroniccomponent including a data array. The first electronic component is in electronic communication with the second electronic component through the first plurality of vertical interconnect channels andthe second plurality of vertical interconnect channels. Providing word lines or bit lines on wafers different from data arrays will provide improved array efficiency, improved routing, and higher scaling flexibility.

Description

technical field [0001] The present disclosure relates generally to three-dimensional electronic memory, and more particularly, to reducing programming current and thermal crosstalk in adjacent memory cells. Background technique [0002] Planar memory cells have been scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication techniques. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. Thus, the memory density of planar memory cells approaches an upper limit. Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. [0003] A 3D cross-point memory is formed when word lines and bit lines are formed perpendicular to each other. The memory cells are formed to be self-aligned at the intersections of WL and BL. The memory cells have the shape of vertical square pillars extending betwee...

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Problems solved by technology

Therefore, the maximum possible density of memory arrays on a wafer is limited by the accommodation of the memory arrays and their bitline contact areas on a single wafer

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