Interconnection test fixture and interconnection test method for silicon adapter plate

Abstract

The invention belongs to the technical field of advanced electronic packaging, and discloses an interconnection test fixture and an interconnection test method for a silicon adapter plate, the test fixture comprises a fixture body and a plurality of silica gel pads, the fixture body is provided with a through hole and a vacuum joint, the inner wall of the through hole is provided with a wafer placing ring, and the wafer placing ring is provided with a plurality of cavities; a vacuum adsorption groove and a plurality of mounting holes are formed in the cavity; a plurality of vacuum holes and aplurality of protrusions are arranged on the silica gel pad, the protrusions are connected with the installation holes respectively, and the vacuum holes are communicated with the vacuum adsorption groove. The test method comprises the following steps: acquiring test data on a to-be-tested silicon adapter plate; according to the test data on the to-be-tested silicon adapter plate, setting the placement position of the silicon adapter plate and loading the to-be-tested silicon adapter plate on the interconnection test fixture; and generating an open-circuit test scheme and a short-circuit testscheme of each test point network for testing. The risk of cracking is effectively avoided, direct testing is adopted, light and reliable contact is guaranteed, product damage is avoided, and subsequent technological machining is not affected.

Description

technical field [0001] The invention belongs to the technical field of advanced electronic packaging, and relates to an interconnection test fixture and an interconnection test method of a silicon adapter board. Background technique [0002] At present, the feature size of integrated circuits is getting closer and closer to the physical limit. It is becoming more and more difficult to continue to increase the integration density by reducing the feature size of the device, and it cannot bring enough dividends in cost and performance. With the continuous development of chip packaging technology, chip integration has changed from a two-dimensional planar arrangement to a three-dimensional stacking method. 2.5D / 3D advanced packaging technology has become the first technology to take on the heavy responsibility of surpassing Moore's Law. The so-called 2.5D refers to that the chips are not packaged first, but are arranged in parallel on the same substrate, and then connected to th...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to overcome the above-mentioned prior art, the shortcoming that the interconnection test of the silicon interposer board is difficult, and provide a kind of interconnection test fixture and the interconnection test method of the silicon interposer board

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