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Protocol conversion bridge circuits, intellectual property cores, and SoCs

A protocol conversion and bridging circuit technology, which is applied in the fields of electrical digital data processing, instruments, computers, etc., can solve the problems of complex high-performance chips, variable debugging and testing requirements, etc., to expand test scenarios, increase test capabilities, and expand access space Effect

Active Publication Date: 2021-04-30
北京燧原智能科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The inventor found in the process of realizing the present invention that the JTAG transmission protocol in the traditional sense and the JTAG network inside the chip have been unable to meet the more complex and changeable debugging of complex high-performance chips in various environments such as test benches and board levels. Testing requirements

Method used

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  • Protocol conversion bridge circuits, intellectual property cores, and SoCs
  • Protocol conversion bridge circuits, intellectual property cores, and SoCs
  • Protocol conversion bridge circuits, intellectual property cores, and SoCs

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0043] Figure 1bA structural diagram of a protocol conversion bridge circuit provided by Embodiment 1 of the present invention. This embodiment is applicable to multiplex the NOC network in the chip for transmission of the pin input signal received by the JTAG pin, so as to realize the on-chip Functional testing of each IP core.

[0044] Such as Figure 1b As shown, the protocol conversion bridge circuit includes: a connected protocol conversion drive circuit 110 and a control signal conversion circuit 120 .

[0045] The protocol conversion driving circuit 110 is configured to receive a JTAG function test signal in the JTAG clock domain from the TAP controller, and convert the JTAG function test signal into an NOC function test signal in the NOC clock domain.

[0046] Wherein, the TAP controller is a TAP state machine, and the TAP controller is directly connected to each JTAG pin. In the prior art, the role of the TAP controller is to convert the JTAG pin input signal rece...

Embodiment 2

[0057] Figure 2a Shows a structural diagram of a protocol conversion bridge circuit in Embodiment 2 of the present invention, as Figure 2a As shown, the protocol conversion driving circuit may specifically include: a data writing module 210 , a data reading module 220 and a first-type configuration register 230 . The control signal conversion circuit may specifically include: a connected function test information generation module 240 and a standard function test signal generation module 250 .

[0058] The data writing module 210 is used to receive the JTAG function test signal from the TAP controller according to the JTAG clock domain, and write the JTAG function test signal into the first type configuration register 230 according to the NOC clock domain;

[0059] The data reading module 220 is configured to read the NOC function test signal matching the JTAG function test signal from the first type configuration register 230 according to the NOC parameters preconfigured i...

Embodiment 3

[0100] exist image 3 A schematic structural diagram of an IP core in Embodiment 3 of the present invention is shown in . Such as image 3 As shown, the IP core includes the protocol conversion bridge circuit described in any embodiment of the present invention.

[0101] Wherein, the protocol conversion bridge circuit includes: a connected protocol conversion drive circuit and a control signal conversion circuit;

[0102] A protocol conversion drive circuit, used to receive the JTAG function test signal in the JTAG clock domain from the TAP controller, and convert the JTAG function test signal into the NOC function test signal in the NOC clock domain;

[0103] The control signal conversion circuit is used to receive the NOC function test signal, and generate at least one function test information according to the NOC function test signal; generate a standard function test signal conforming to the NOC standard protocol according to the at least one function test information. ...

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Abstract

The invention discloses a protocol conversion bridge circuit, an intellectual property core and a system level chip. The protocol conversion bridging circuit includes: a connected protocol conversion drive circuit and a control signal conversion circuit; a protocol conversion drive circuit for receiving the JTAG function test signal in the JTAG clock domain from the TAP controller, and converting the JTAG function test signal to The NOC function test signal in the NOC clock domain; the control signal conversion circuit is used to receive the NOC function test signal, and generate at least one function test information according to the NOC function test signal; generate at least one function test information according to Standard functional test signal of NOC standard protocol. The technical solution of the embodiment of the present invention realizes the technical effect of performing functional testing on each IP core in the chip through the pin input signal received by the JTAG pin.

Description

technical field [0001] The embodiment of the present invention relates to computer hardware technology, in particular to chip testing technology, and in particular to a protocol conversion bridge circuit, an intellectual property core and a system-level chip. Background technique [0002] With high performance, the functions of large-scale chips are becoming increasingly complex, and dozens or even hundreds of IP (Intellectual Property, intellectual property) cores may be carried in the same chip at the same time. This kind of complex high-performance chip puts forward higher requirements for testing machine and board-level testing and debugging. [0003] The JTAG (Joint Test Action Group, joint test working group) network and test logic inside the traditional chip are as follows: Figure 1a shown in Figure 1a , the chip receives the JTAG pin input signal through the JTAG pin, and the test access port (Test Access Port, TAP) controller converts the JTAG pin input signal int...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/38G06F13/40G06F11/263G06F15/78
CPCG06F11/263G06F13/382G06F13/4022G06F15/7825G06F2213/3852
Inventor 马海英
Owner 北京燧原智能科技有限公司