A kind of demodulation system and demodulation method of msk digital baseband signal
A demodulation system and signal technology, which is applied in the demodulation system field of MSK digital baseband signals, can solve the problems of large consumption of general logic resources, inability to ensure the distribution of realization results, small area, etc., and achieve low power consumption, reliable operation, and small area. area effect
Active Publication Date: 2021-08-31
SICHUAN JIUZHOU ELECTRIC GROUP
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[0003] In view of the above analysis, the present invention aims to provide a demodulation system and demodulation method for MSK digital baseband signals, to solve the problem that the current MSK baseband demodulation algorithm consumes a lot of general logic resources, and cannot ensure that the realization results are distributed in smaller area problem
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[0105] Preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of the application and together with the embodiments of the present invention are used to explain the principle of the present invention and are not intended to limit the scope of the present invention.
[0106] The technical idea of the present invention: In addition to general logic resources, FPAG also has two special-purpose components, that is, BLOCK RAM for dense storage and DSP48E1 chip for high-speed arithmetic. These two resources are integrated in the logic array by columns , are embedded in logic sections and tend to be close to each other. It is especially suitable for implementing intensive calculation closely related to storing data in memory, such as MSK digital baseband demodulation algorithm. On the one hand, the technical solution of the present invention specifies BLOCK RA...
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The present invention relates to a demodulation system and demodulation method of MSK digital baseband signal. FPGA-based logic resource block executes algorithm module. Logic resource block includes BLOCK RAM and DSP48E1. Algorithm module includes control unit, reference signal generation unit, multiply-accumulate Unit and demodulation processing unit; the control unit generates four-quadrant clockwise / counterclockwise I / Q channel reference signals based on the single-port BLOCK RAM for storing reference signals; the multiplication and accumulation unit obtains clockwise / counterclockwise I / Q channel multiplication and accumulation; the multiplication and accumulation unit includes Using 6 DSP48E1 cascades to realize clockwise / counterclockwise I / Q multiplication and accumulation components; the control unit outputs clockwise / counterclockwise multiplication and accumulation to the demodulation processing unit based on the system clock and demodulation trigger instructions; demodulation The processing unit completes data demodulation based on the dual-port BLOCK RAM that stores demodulation information. At the same time, a demodulation method based on the above-mentioned demodulation system is disclosed. The invention solves the problem that the current MSK baseband demodulation algorithm consumes a lot of general logic resources and cannot ensure that the results are distributed in a small area.
Description
technical field [0001] The invention relates to the technical field of modulation and demodulation, in particular to a demodulation system and method for MSK digital baseband signals. Background technique [0002] MSK (Minimum Frequency Shift Keying) signal is a FSK (Frequency Shift Keying) signal with constant envelope, continuous phase, minimum bandwidth and strict orthogonality. The FPGA implementation of the MSK baseband demodulation algorithm is usually based on the multiplier IP core and distributed RAM. Whether it is to build a memory equivalent to the size of BLOCK RAM, or at least 24 multipliers and 24 adders required by the MSK baseband demodulation algorithm, a large number of look-up tables and flip-flops in multiple configurable logic blocks are required and other resources, the wiring delay caused by the distribution of the implementation results on a large area will obviously limit the timing performance of the algorithm, that is to say, the clock frequency t...
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IPC IPC(8): H04L27/10H04L27/14
CPCH04L27/106H04L27/14
Inventor 朱爱红何敏王维刚
Owner SICHUAN JIUZHOU ELECTRIC GROUP