A Lightweight Software Debugging Method for Heterogeneous Many-Core Processors

A technology for many-core processors and software debugging, applied in software testing/debugging, electrical digital data processing, instruments, etc., can solve problems such as high debugging technical costs, reduce debugging time and space costs, and save computing resources Effect

Active Publication Date: 2022-07-12
JIANGNAN INST OF COMPUTING TECH
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Problems solved by technology

[0006] The purpose of the present invention is to provide a lightweight software debugging method for heterogeneous many-core processors. This debugging technology can not only solve the debugging problem of heterogeneous many-core processors, but also solve the problem of excessive overhead of traditional debugging techniques.

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  • A Lightweight Software Debugging Method for Heterogeneous Many-Core Processors

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Embodiment

[0038] Embodiment: A lightweight software debugging method for heterogeneous many-core processors, refer to the appendix figure 1 , based on heterogeneous many-core processors, including the following steps:

[0039] S1: Input debugging command: input the debugging command of the master core and the slave core in the unified syntax format and compatible with multi-core;

[0040] Here, the debugging function is implemented according to the syntax format of the multi-core debugging tool, so that both the master core and the slave core on the heterogeneous chips support this syntax format, so that the user can learn the same syntax format while saving time, so that they can master the debugging method.

[0041] S2: Address space positioning: According to the symbol table about debugging information provided by the compiler and language, process the input debugging commands, and convert source-level symbols into logical addresses in the process address space;

[0042] Among them,...

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Abstract

The invention discloses a lightweight software debugging method for heterogeneous many-core processors. Based on the heterogeneous many-core processors, the method includes the following steps: S1: inputting a debugging command: inputting the unified syntax format of the master core and the slave core, and combining Compatible with multi-core debugging commands; S2: Address space positioning: According to the symbol table about debugging information provided by the compiler and language, process the input debugging commands, and convert source-level symbols into logical addresses in the process address space; S3: Execution control ;S4: debugging interrupt processing; S5: debugging signal processing; S6: program on-site processing: the debugger process realizes consistent debugging of the master and slave cores according to the sub-section debugging information of the unified logical address space of the many-core program and the unified thread debugging queue . The present invention satisfies the requirement of heterogeneous many-core software debugging, reduces debugging overhead, and effectively saves computing resources.

Description

technical field [0001] The invention belongs to the technical field of optimization of heterogeneous many-core processors, and in particular relates to a lightweight software debugging method for heterogeneous many-core processors. Background technique [0002] In the multi-core processor software ecosystem, a shared programming model is used for parallel development, and the multi-thread sharing method is specified through pragmas. The OS (operating system) provides a standard debugging interface for processes and threads, and debugging tools for commercial and open source versions are available. Both can support the debugging of multi-core parallel programs. [0003] At present, a small number of main cores and a large number of slave cores are integrated on the domestic Shenwei multi-core processor chip. The operating system runs on the main core, and the simplified design of the slave core does not run the operating system. The compiler connects the master core instruct...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/36G06F9/50
CPCG06F11/3672G06F9/5027G06F9/5066
Inventor 彭达佳王敬宇刘勇陈华蓉宋佳伟冯赟龙孙川罗威张威梁艳
Owner JIANGNAN INST OF COMPUTING TECH
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