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Method and processor for ensuring data crash consistency in secure non-volatile memory

A non-volatile and consistent technology, applied in the direction of electrical digital data processing, memory system, memory address/allocation/relocation, etc., can solve the problems of high transaction execution delay and write amplification that cannot be effectively balanced, so as to avoid persistence Sequence constraints, the effect of reducing execution delay

Active Publication Date: 2022-05-24
HUAZHONG UNIV OF SCI & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The present invention provides a method and a processor for ensuring data crash consistency in a secure non-volatile memory, which are used to solve the problem of high transaction execution delay and write amplification when balancing the security of non-volatile memory and data crash consistency. Phenomena that lead to technical problems that cannot be effectively balanced

Method used

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  • Method and processor for ensuring data crash consistency in secure non-volatile memory
  • Method and processor for ensuring data crash consistency in secure non-volatile memory
  • Method and processor for ensuring data crash consistency in secure non-volatile memory

Examples

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Embodiment 1

[0039] A way to guarantee data crash consistency in safe non-volatile memory, such as figure 1 As shown, including: adding a transaction persistence sequence control engine to the first-level cache controller of the processor; adding three registers to the memory controller to store the ciphertext data, counter blocks and default values ​​that need to be written to the memory together Kerr tree sub-bottom node, and the steps of the above processor processing transactions include:

[0040] (1) The transaction persistence sequence control engine controls the flushing and kicking operations of transaction logs and data in the first-level data cache. The flushing and kicking operations of the transaction log cache lines are immediately persisted (that is, written) to the memory. method, the refresh operation of the transaction data cache line adopts the method of first persisting the corresponding log cache line in the first-level data cache and then persisting the data cache line...

Embodiment 2

[0055] A processor for ensuring data crash consistency in secure non-volatile memory, comprising: a processor core, a first-level data cache, a first-level cache controller, and a memory controller, wherein the first-level cache controller includes a transaction persistence sequence The control engine; the memory controller includes three registers for storing the ciphertext data, the counter block and the sub-bottom node of the Merkle tree that need to be persisted to the memory together; among them,

[0056] The transaction persistence sequence control engine is used to control the refresh and eject operations of transaction logs and data in the first-level data cache. The line refresh operation adopts the method of first writing the corresponding log cache line in the first-level data cache into the memory, and then writing the data cache line into the memory;

[0057] Each time the memory controller writes the transactional memory, it sequentially increments the secondary ...

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Abstract

The invention belongs to the field of computer data storage, and specifically relates to a method and a processor for ensuring data crash consistency in a safe non-volatile memory, including: adding a transaction persistence sequence control engine to a first-level cache controller to control transactions in logs and The order of data persistence. The engine refreshes and kicks out the log cache line by immediately persisting it to the memory. For the refresh operation of the data cache line, it first persists the corresponding log cache line in the cache and then persists the data cache. way; the memory controller receives write requests from the cache, persists the data, counter blocks, and sub-bottom nodes of the Merkle tree in advance without waiting for the Merkle tree to be completely updated, and writes the secondary counters and log entries in parallel According to the address information, write security metadata is merged in the write queue. The invention ensures the balance between safety and crash consistency of the non-volatile memory system, reduces transaction execution delay and improves system write life.

Description

technical field [0001] The invention belongs to the field of computer data storage, and more particularly, relates to a method and a processor for ensuring data crash consistency in a secure non-volatile memory. Background technique [0002] The traditional memory technology DRAM is limited by the manufacturing process and refresh power consumption, and it is difficult to provide a larger capacity to meet the memory requirements of computer systems in the era of big data. New non-volatile memory technologies (NVM), such as phase-change memory (PCM), resistive-variable memory (ReRAM), and self-transfer torque random access memory (STT-RAM), have non-volatile and DRAM-like performance. It has high storage density and low energy consumption, and is expected to become the next-generation memory technology. And with the release of Intel Optane DCPersistent Memory, non-volatile memory technology will be widely deployed. [0003] Due to non-volatility, there are two challenges to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02G06F12/0811G06F11/34
CPCG06F12/0238G06F12/0811G06F11/3476
Inventor 华宇李璇徐豪陈章玉
Owner HUAZHONG UNIV OF SCI & TECH
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