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LIO bus extension UART peripheral system and method based on FPGA

A bus and bus protocol technology, applied in the field of LIO bus extended UART peripheral system, can solve the problem of no extended UART, etc., and achieve the effects of avoiding interface level conflicts, strong practicability, and simple structure

Inactive Publication Date: 2021-03-26
SUZHOU CHANGFENG AVIATION ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, in the public technology, for the LIO peripheral expansion of 2k1000, only the DMA controller is extended, and there is no expansion of UART, IIC, HDLC and other peripherals.

Method used

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  • LIO bus extension UART peripheral system and method based on FPGA
  • LIO bus extension UART peripheral system and method based on FPGA
  • LIO bus extension UART peripheral system and method based on FPGA

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Embodiment Construction

[0047] Embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0048] Embodiments of the present disclosure are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Apparently, the described embodiments are only some of the embodiments of the present disclosure, not all of them. The present disclosure can also be implemented or applied through different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, a...

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Abstract

The invention provides an LIO bus extension UART peripheral system and method based on an FPGA. The system comprises a Loongson 2k1000 module, and an LIO port of the Loongson 2k1000 module is connected with an FPGA module; the FPGA module comprises a bus protocol analysis unit which is used for analyzing an LIO bus protocol of the Loongson 2K1000 processor and realizing an LIO communication function of the FPGA and the Loongson 2K1000 processor; the control unit is used for realizing read-write operation of the FIFO and comprises a read control logic, a write control logic, a read FIFO Read FIFO and a write FIFO Write FIFO; a UART unit is used for completing sending and receiving of a UART protocol. According to the method, the occasion that more UART peripheral resources are needed by theLoongson 2k1000 can be met, universal peripheral expansion can be easily conducted through the method, and the method has the advantages of being simple in structure, high in universality, high in practicability and the like.

Description

technical field [0001] The present disclosure relates to the technical field of bus expansion and storage control, in particular to an FPGA-based LIO bus expansion UART peripheral system and method. Background technique [0002] The LocalIO bus, referred to as the LIO bus, is a peripheral access interface provided by the Loongson 2k1000 series CPU. It is generally used to connect an external ROM for system startup. Loongson 2k1000 series CPU, as a domestic self-developed CPU, is widely used in some products with localization requirements. The CPU processor has limited peripheral resources. If you encounter some special application scenarios, you need more peripheral interfaces, but the 2k1000 processor cannot provide more peripheral interfaces. At this time, you need to expand the peripheral interfaces of the CPU. . At present, in the public technology, only the DMA controller is extended for the LIO peripheral expansion of 2k1000, and there is no expansion of UART, IIC, H...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38G06F5/06
CPCG06F5/06G06F13/385
Inventor 杨炳伟程骥思孙冲樊涛
Owner SUZHOU CHANGFENG AVIATION ELECTRONICS