Multi-thread comprehensive method and device

A synthesis method and multi-thread technology, applied in the FPGA field, can solve problems such as long running time and affecting the execution efficiency of FPGA synthesis tools

Active Publication Date: 2021-03-30
GOWIN SEMICON CORP LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Practice has found that when FPGA synthesis tools synthesize these large-scale netlists, they need to rely on the CPU on the computer. When using traditional netlist s

Method used

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  • Multi-thread comprehensive method and device

Examples

Experimental program
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Embodiment 1

[0097] see figure 1 , figure 1 It is a schematic flowchart of a multi-thread synthesis method disclosed in an embodiment of the present invention. in, figure 1 The described method can be applied to an FPGA synthesis tool, which is not limited in the embodiment of the present invention. Such as figure 1 As shown, the method may include the following operations:

[0098] 101. The FPGA synthesis tool splits the original netlist according to the determined split parameters to obtain at least two subnetlists corresponding to the original netlist.

[0099] In the embodiment of the present invention, the original netlist is obtained by parsing the RTL design file, wherein the original netlist is a circuit-level netlist. Optionally, the split parameter is used to realize the split control of the original netlist, which may include the total number N of subnetlists obtained by splitting, that is, the FPGA synthesis tool splits the original netlist to obtain N subnets In the tabl...

Embodiment 2

[0131] see image 3 , image 3 It is a schematic flowchart of another multi-thread synthesis method disclosed in the embodiment of the present invention. in, image 3 The described method can be applied to an FPGA synthesis tool, which is not limited in the embodiment of the present invention. Such as image 3 As shown, the method may include the following operations:

[0132] 201. The FPGA synthesis tool splits the original netlist according to the determined split parameters to obtain at least two subnetlists corresponding to the original netlist.

[0133] 202. The FPGA synthesis tool creates at least two sub-threads according to all sub-netlists, and starts all created sub-threads to perform synthesis operations on all sub-netlists in parallel to obtain a synthesized sub-netlist corresponding to each sub-netlist.

[0134] 203. The FPGA synthesis tool merges the synthesized subnetlists corresponding to all the subnetlists to obtain the synthesized netlist corresponding ...

Embodiment 3

[0168] see Figure 4 , Figure 4 It is a schematic structural diagram of a multi-thread synthesis device disclosed in an embodiment of the present invention. in, Figure 4 The described multi-thread synthesis device can be applied to an FPGA synthesis tool, which is not limited in the embodiment of the present invention. Such as Figure 4 As shown, the multi-thread synthesis device may include:

[0169] The splitting module 301 is configured to split the original netlist according to the determined splitting parameters to obtain at least two subnetlists corresponding to the original netlist.

[0170] The creating module 302 is configured to create at least two sub-threads according to all subnet lists.

[0171] The parallel synthesis module 303 is configured to start all the created sub-threads to perform synthesis operations on all subnets in parallel to obtain the synthesized subnet corresponding to each subnet.

[0172] The merging module 304 is configured to merge th...

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Abstract

The invention discloses a multi-thread integration method and device, and the method comprises the steps: splitting an original netlist according to determined splitting parameters, and obtaining at least two sub-netlists corresponding to the original netlist; creating at least two sub-threads according to all sub-net tables obtained by splitting; starting all the created sub-threads to execute comprehensive operation on all the sub-netlists in parallel to obtain a comprehensive sub-netlist corresponding to each sub-netlist; and combining the integrated sub-netlists corresponding to all the sub-netlists to obtain an integrated netlist corresponding to the original netlist. Therefore, the original netlist can be split into at least two sub-netlists, and all the sub-netlists are subjected toparallel integration through the created sub-threads, so the execution efficiency of the FPGA integration tool is improved, and the development and design efficiency of the FPGA is improved.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to a multi-thread synthesis method and device. Background technique [0002] In the FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) design process, the netlist (netlist) is a text file used to describe the connection relationship between circuit elements. A complex netlist can be understood as consisting of several It consists of a module with typical logic functions and a control circuit. Among them, common modules include registers, counters, arithmetic and logic operation units, memories, etc. [0003] With the development of the FPGA industry, the scale of netlists has become larger and larger, and netlists of millions or even tens of millions of units emerge in endlessly. Practice has found that when FPGA synthesis tools synthesize these large-scale netlists, they need to rely on the CPU on the computer. When using traditional netlist synthesis methods to syn...

Claims

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Application Information

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IPC IPC(8): G06F30/343
CPCG06F30/343
Inventor 王宁李元策刘奎张青
Owner GOWIN SEMICON CORP LTD
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