FPGA embedded PCIExpressIP core mass production test optimization method based on coverage rate sorting

Abstract

The invention relates to an FPGA embedded PCI Express IP core mass production test optimization method based on coverage rate sorting. The method comprises the following specific steps: step 1, generating a test vector set required by an FPGA embedded PCI Express IP core test; 2, performing node coverage rate measurement and calculation on each test vector in the test vector set by using a test vector node coverage rate statistical algorithm; 3, obtaining a single test vector with the highest node coverage rate in the test vector set from the step 2; and 4, performing sorting optimization on the original test vector set based on the single test vector obtained in the step 3 by using a test vector set sorting algorithm to finish optimization of the test vector set. Through the above steps,on the premise of not reducing the test coverage rate, the batch production test optimization method based on coverage rate sorting is adopted to complete sorting optimization of the test vector set,the test efficiency of the test vector set can be effectively improved, the configuration test time is shortened, and the configuration test cost is reduced.

Description

technical field [0001] The invention relates to an FPGA embedded PCI Express IP core mass production test optimization method, which belongs to the technical field of integrated circuits. Background technique [0002] With the continuous development of Field Programmable Logic Gate Array (namely FPGA), the types and quantities of IP modules embedded in FPGA are also increasing, and the testing of FPGA has also brought more new difficulties and challenges. [0003] In recent years, in the process of designing and developing FPGAs, the proportion of testing costs in the total cost is getting higher and higher, and the testing time for FPGA internal interconnection resources and IP core modules also occupies the vast majority of the total development time. In particular, compared to the internal interconnection resources of the FPGA, the FPGA embedded IP core has a more complex internal structure and design principles, which not only makes the test more difficult, but also occu...

AI Technical Summary

Problems solved by technology

[0007] The technical problem to be solved by the present invention is: in order to solve the code flow configuration time of FPGA embedded PCI Express IP core test process is long, the problem of low test efficiency, the present invention proposes a kind of FPGA embedded PCIExpress IP core based on coverage rate sorting Mass production test optimization method

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