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Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions

A technology for storing instructions and caching, applied in the field of exclusive cache coherency state, which can solve problems such as performance degradation, failure to make progress, waste of power, etc., to achieve the effects of reducing delay, reducing power, and improving system performance

Pending Publication Date: 2021-04-02
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This results in undesired performance degradation of the system and wastes power as computing devices must remain active but cannot make progress

Method used

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  • Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions
  • Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions
  • Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions

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Embodiment Construction

[0018] Aspects of the inventive teachings herein are disclosed in the following description and associated drawings directed to certain aspects. Alternative aspects may be devised without departing from the scope of the inventive concepts herein. Additionally, well-known elements of the environments may not be described in detail or may be omitted so as not to obscure the relevant details of the inventive teachings herein.

[0019] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term "aspects of the invention" does not require that all aspects of the invention include the discussed feature, advantage or mode of operation.

[0020] The terminology used herein is for the purpose of describing particular aspects only and is not intended to limit aspects of the invention. As used herein, the ...

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PUM

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Abstract

A method, an apparatus, and a system for prefetching exclusive cache coherence state for store instructions is disclosed. The apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configuredto determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.

Description

[0001] priority claim [0002] This patent application claims priority to nonprovisional application serial number 16 / 113,120, filed August 27, 2018, and entitled "Method, Apparatus, and System for Exclusive Cache Coherency State for Prefetching Store Instructions" , which application is assigned to the assignee of the present application and is hereby expressly incorporated by reference. technical field [0003] Aspects of the disclosure relate generally to store instructions, and more specifically to exclusive cache coherency states for prefetching store instructions. Background technique [0004] A computing device may execute memory access instructions (eg, load instructions and store instructions) as part of normal processing operations. In the case of a computing device with multiple central processing units (CPUs), the computing device may implement a hardware coherency protocol to ensure that any associated cache memory and system memory shared among the multiple C...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/0888G06F12/0817
CPCG06F12/0888G06F12/0824Y02D10/00G06F3/0611G06F3/0631G06F3/0656G06F3/0673G06F12/0815G06F2212/1024G06F2212/604G06F12/0862G06F12/0871
Inventor L·颜N·乔杜里P·戈沙尔T·P·施派尔B·M·斯坦普尔W·J·麦卡沃伊P·埃比勒
Owner QUALCOMM INC