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Parallel data processing method and parallel processor for effectively eliminating data access delay

A data access and data processing technology, applied in the fields of electrical digital data processing, concurrent instruction execution, instruments, etc., can solve problems such as excessive energy consumption, parallel processors cannot adapt well to task characteristics, and task switching costs are high, and reduce the cost of task switching. Waste and energy consumption, good task switching cost and branch jump cost, and the effect of reducing task switching cost and branch jump cost

Pending Publication Date: 2021-04-30
SHENZHEN ZHONGWEIDIAN TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when there are relatively many data access instructions, and the calculation instructions and the maximum number of threads cannot cover up the delay, the parallel processor cannot adapt to the task characteristics well, resulting in high task switching costs, waste of computing resources and excessive energy consumption

Method used

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  • Parallel data processing method and parallel processor for effectively eliminating data access delay
  • Parallel data processing method and parallel processor for effectively eliminating data access delay

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Embodiment Construction

[0031] The present invention will be further described below in conjunction with the description of the drawings and specific embodiments.

[0032] The invention provides a new parallel data processing method and a parallel processor for effectively eliminating data access delay, which can realize the minimum task switching cost and the minimum branch jump cost.

[0033] A parallel data processing method for effectively eliminating data access delays, comprising the steps of: dividing data that can be processed in parallel into several WORKGROUPs (working groups), and setting necessary parameters for each WORKGROUP (working group); starting multithreading for processing, each Each thread processes a WORKITEM (work item); if it encounters data that needs to be accessed by external memory, save the necessary context, the current thread sleeps and waits, and the hardware switches to the next thread and performs calculations; after the data is returned, the thread is notified to en...

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Abstract

The invention provides a parallel data processing method for effectively eliminating data access delay, and the method comprises the following steps: dividing data capable of being processed in parallel into a plurality of working groups, and setting parameters for each working group; starting multiple threads for processing, wherein each thread processes one work item; If data needing to be accessed to the external memory is encountered, storing the contexts, enabling the current thread to be in dormancy waiting, switching hardware to the next thread, and carrying out operation; after the data is returned, notifying the dormant waiting thread to enter switching waiting at any time, and once hardware resources are released, carrying out the recalculation immediately. The invention further provides a parallel processor. The invention has the beneficial effects that the task switching cost and the branch skipping cost can be well reduced, and the waste of computing resources and the consumption of energy are reduced.

Description

technical field [0001] The invention relates to a processor, in particular to a parallel data processing method and a parallel processor for effectively eliminating data access delay. Background technique [0002] At present, the task switching cost of the existing parallel data processing method is relatively high. For example, the Chinese patent No. 200910190339.1, a parallel processor and its thread processing method, discloses a MVP (Multi-thread Virtual Pipeline, multi-threaded virtual pipeline) processor, which can effectively deal with a large number of parallel tasks, and has a high cost performance. However, when there are relatively many data access instructions, and the computing instructions and the maximum number of threads cannot hide the delay, the parallel processor cannot adapt to the task characteristics well, resulting in high task switching costs, waste of computing resources and excessive consumption of energy. Contents of the invention [0003] In or...

Claims

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Application Information

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IPC IPC(8): G06F9/46G06F9/50G06F9/38
CPCG06F9/461G06F9/5027G06F9/3814G06F9/3869G06F2209/5018Y02D10/00
Inventor 钟伟冀谦祥梅思行
Owner SHENZHEN ZHONGWEIDIAN TECH