An ultra-wideband chip bias circuit structure
A bias circuit and ultra-wideband technology, which is applied to amplifiers, electrical components, amplifiers, etc. Performance-enhancing effects
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Embodiment 1
[0044] This embodiment provides an ultra-wideband chip bias circuit structure, including a current source, an equivalent inductor, a microstrip line, a chip decoupling capacitor, and a spiral inductor. One end of the current source is grounded, and the other end is connected in series through an equivalent inductor Microstrip line, one end of the on-chip decoupling capacitor is grounded through the spiral inductor, and the other end is connected to the connection line between the equivalent inductor and the microstrip line.
[0045] This embodiment also provides a single-stage RF power amplifier applying the ultra-wideband chip bias circuit structure, such as figure 1 shown, including source Z S1 , input matching network, stabilization network, transistor, output matching network, load Z L1 , gate bias circuit and drain bias circuit;
[0046] The input matching network includes a first microstrip line MLIN 1 , the second microstrip line MLIN 2 , the first capacitor C 1 an...
Embodiment 2
[0056] This embodiment provides a six-stage distributed amplifier using an ultra-wideband chip bias circuit structure, such as figure 2 shown, including source Z S2 , gate artificial transmission line, stabilization network, first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 , drain artificial transmission line, load Z L2 , gate bias circuit and drain bias circuit.
[0057] The gate artificial transmission line includes an eighth capacitor C 8 , the fourteenth microstrip line MLIN 14 , the fifteenth microstrip line MLIN 15 , the sixteenth microstrip line MLIN 16 , the seventeenth microstrip line MLIN 17 and the eighteenth microstrip line MLIN 18 ; The eighth capacitor C 8 one end through the signal source Z S1 Ground, the other end goes through the fourteenth microstrip line MLIN 14 , the fifteenth microstrip line MLIN 15 , the sixteenth microstrip line M...
Embodiment 3
[0067] This embodiment provides a two-stage low-noise amplifier using an ultra-wideband chip bias circuit structure, such as image 3 shown, including source Z S3 , load Z L3 , input matching network, first stabilization network, second stabilization network, seventh transistor M 7 , the eighth transistor M 8 , an inter-stage matching network, an output matching network, a first gate bias circuit, a second gate bias circuit, a first drain bias circuit and a second drain bias circuit;
[0068] The input matching network includes an eighteenth capacitor C 18 and the twelfth inductance L 12 ; The eighteenth capacitor C 18 one end is connected to the signal source Z S3 , the other end passes through the twelfth inductor L 12 connected in series to the seventh transistor M 7 the grid;
[0069] The first gate bias circuit includes a first gate current source Vg3, a first gate equivalent inductance L 10 , the nineteenth capacitor C 19 , the first grid spiral inductance L ...
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