Chip power consumption adjustment method and device, electronic equipment and storage medium

Abstract

The invention provides a chip power consumption adjusting method. The method comprises the following steps: acquiring a module usage rate of a module of a chip; determining a clock frequency corresponding to the module according to the usage rate of the module; and adjusting the current clock frequency of the module to be the clock frequency so as to adjust the power consumption of the module. It can be seen that the chip power consumption adjusting method is designed in the chip front-end design stage, the clock frequency is determined according to the module usage rates of all the modules of the chip, the current clock frequency can be dynamically adjusted according to the different module usage rates, and therefore chip power consumption is effectively reduced. The invention further provides a chip power consumption adjusting device, electronic equipment and a storage medium which all have the above beneficial effects.

Description

technical field [0001] The present application relates to the technical field of chip power consumption control, and in particular to a chip power consumption adjustment method, device, electronic equipment and storage medium. Background technique [0002] With the development of integrated circuit design scale and manufacturing process, power consumption has become an important indicator of chips. Excessive power consumption has a great impact on the performance and cost of chips. Especially with the rapid development of mobile devices, more attention is paid to chip power consumption. Obviously, low-power chip design has become an essential link. [0003] At present, most of the methods to reduce chip power consumption are to automatically insert units such as gating clocks through tools in the layout and wiring stage of the chip back-end to reduce power consumption, which cannot be particularly effective in reducing chip power consumption. [0004] Therefore, how to prov...

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Problems solved by technology

[0003] At present, most of the methods to reduce chip power consumption are to automatically insert units such as gating clocks through tools in the layout and wiring stage of the chip back-end to reduce power consumption, which cannot be particularly effective in reducing chip power consumption.

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